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系統識別號 U0026-0812200911141080
論文名稱(中文) SoC介面IP之系統化設計與實現
論文名稱(英文) Systematic Design and Implementation of SoC Interface IPs
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 92
學期 2
出版年 93
研究生(中文) 吳源晉
研究生(英文) Yuan-Chin Wu
電子信箱 andrea@j92a21.ee.ncku.edu.tw
學號 n2691470
學位類別 碩士
語文別 英文
論文頁數 102頁
口試委員 口試委員-紀新洲
口試委員-蔣元隆
指導教授-周哲民
口試委員-陳培殷
口試委員-鄺獻榮
中文關鍵字 介面設計 
英文關鍵字 interface design  interface synthesis  interface architecture 
學科別分類
中文摘要   在System-on-Chip(SoC)時代,重覆使用矽智財(Intellectual Property, IP)來建構系統是設計方法。然而,不同供應商發展的IP常由於介面規格不同導致設計整合上的困難,更影響了產品上市(Time-to-Market)的時間,因此介面間的設計轉換就成了重要議題。在這篇論文中將提供一個完整的設計方式,取代原本繁雜且要不斷重覆的設計過程,取而代之,當一毎介面的通訊協定完整描述後,透過設計方法論做協定轉換、且以高階合成技巧利用通訊時序圖的建構,使得不同介面間的轉換變得更為簡潔。配合此設計流程使用了一硬體架構,除了便於滿足每個不同介面通訊需求,更提供了自動化設計的可能性。這篇論文主要作用是提高了介面設計的抽象層度,並且以自動化減少設計者在建構系統時為滿足各種介面所花的成本。
  本論文除了對此設計流程及其所討論議題將有所呈述,並且以PCI-AHB(AMBA)橋接器設計為一範例,透過設計流程將兩個不同架構的通訊協定標準做轉換,並且套用到此硬體架構上,來完成一個橋接器的設計;透過這方式,它帶來的好處在於方便驗証且在做錯誤修正時,能在細部調整就能達到要求的效果。


英文摘要   In system-on-chip (SoC) design, design methodologies rely heavily on reuse of intellectual property (IP) blocks. Since most IPs are provided by different vendors, they have different interface schemes, and different data rates. A hardware module, like a wrapper, would be necessary to interact with these IPs for transferring information and synchronizing their inputs and outputs. In order to automate design reuse, an interface synthesis approach will be proposed in this thesis which describes a methodology for interface process generation and protocol dual translation, also adopts a interface architecture using queues for data transfer between incompatible protocols. The main effort of this thesis is to raise the interface design abstraction and to promote interface synthesis automation for each two incompatible protocols.
  Base on the interface architecture and the synthesis methodology, the design flow is illustrated through a point-to-point communication bridge between two standard protocols, Peripheral Component Interconnect (PCI) and AHB, AMBA. Any interface design, like PCI-AHB Bridge, would be easily debugged, verified and highly portable in a SoC system.


論文目次 Chapter 1. Introduction ……………………………………… 1
1.1 Reuse of Intellectual Property …………………………… 2
1.2 Why the Wrapper Design Necessary ………………………… 3
1.3 Goal of the Paper …………………………………………… 4
1.4 Paper Organization …………………………………………… 5

Chapter 2. Perspectives of Interface design ……………… 6
2.1 Interface Design …………………………………………… 7
2.2 Wrapper Design ……………………………………………… 8
2.3 Perspectives of Wrapper Flow Control/Management … 11
2.3.1 Synchronization ………………………………………… 13
2.3.2 Buffering Mechanism …………………………………… 14
2.3.3 Bitwidth Conversion …………………………………… 15
2.3.4 Control Classifications and Considerations …… 17
2.3.5 Address Transfer ……………………………………… 18
2.3.6 Latency ………………………………………………… 19

Chapter3. The Interface Design Framework ………………… 22
3.1 What’s the Design Framework About? ………………… 23
3.2 Proposed Interface Architecture ……………………… 25
3.2.1 Communication Scheme ………………………………… 26
3.2.2 Queue Model ……………………………………………… 28
3.3 What is Interface Synthesis …………………………… 30
3.3.1 Interface Synthesis Algorithm ……………………… 32
3.4 Synthesis Flow …………………………………………… 34
3.4.1 Problem Statement ……………………………………… 34
3.4.2 Generation of Interface synthesis Process ……… 35
3.4.2.1 Protocol Description and Presentation as Ordered
Relation ………… 39
3.4.2.1.1 Operation Definition ……………………………… 36
3.4.2.2 Partitioning Relation Blocks into Groups ……… 37
3.4.2.3 Interface Process Generating ……………………… 37
3.4.3 Protocol Sequence Graph ……………………………… 40
3.4.4 FSMs and Architecture Mapping ………………………… 42

Chapter 4. Example – PCI-AHB Wrapper Design ……… 43
4.1 PCI-AHB Bridge ……………………………………………… 44
4.1.1 General Description …………………………………… 44
4.1.2 Features …………………………………………………… 45
4.2 PCI Specification ………………………………………… 45
4.2.1 Configuration Register ………………………………… 46
4.2.1.1 Device Identification ……………………………… 47
4.2.1.2 Device Control and Status …………………………… 48
4.2.1.3 Base Address ……………………………………… 49
4.2.2 Signal Definition ……………………………………… 50
4.2.3 Transfer Operation of PCI Bus ……………………… 51
4.3 AHB Specification ………………………………………… 53
4.3.1 AMBA System ……………………………………………… 53
4.3.2 AHB Bus Interconnection ……………………………… 53
4.3.3 Signal Definition ……………………………………… 55
4.4.3.1 Arbitration Signals ………………………………… 57
4.3.4 Basic and Burst Transfer of AHB …………………… 58
4.3.4.1 Address Decoding ……………………………………… 60
4.3.5 Transfer Type and Slave Response Type …………… 61
4.4 Design Descriptions and Implementation …………… 63
4.4.1 Transfer Mechanism ……………………………………… 64
4.4.1.1 Burst Transfer ………………………………………… 64
4.4.1.2 Responsibility of FSMs ……………………………… 66
4.4.1.3 Handshaking between FSMs …………………………… 68
4.4.1.4 Read/Write Transfer ………………………………… 69
4.4.2 Transfer Protection …………………………………… 72
4.4.3 Implementation Flow …………………………………… 73
4.4.3.1 FSM with Functional Blocks ……………………… 73
4.4.3.2 Interface Generation ……………………………… 76
4.4.3.2.1 Representing Protocols as Order Relations … 77
4.4.3.2.2 Presenting Blocks with PSG …………………… 78
4.4.3.2.3 Generating the Interface ………………………… 81
4.4.3.2.4 Interconnect Optimization and PSG Merge …… 86
4.4.3.2.5 Generate the FSM from PSG ……………………… 88
4.5 Simulation Result ………………………………………… 89

Chapter 5. Further work ………… ………………………… 93
5.1 Interface Design from Reconfiguration to Automation … 94
5.2 Early Stage Simulation and Validation ……………… 95
5.3 Low-Power Consideration ………………………………… 96
5.4 Wrapped in Test …………………………………………… 97

Chapter 6. Conclusion ………………………………………… 98

Reference ………………………………………………………… 100

參考文獻 [1] Roberto Passerone, James A. Rowson. “ Automatic Synthesis of Interfaces between Incompatible Protocols ”. Proceedings of the 35th annual conference
on Design Automation Conference, DAC 98, 1998.
[2] G. Borriello. “ A New Interface Specification Methodology and its Applications to Transducer Synthesis “. PhD thesis, University of California at Berkeley, Berkeley CA, 1988.
[3] Dognwan Shin and Daniel Gajski. “Interface Synthesis from Protocol Specification” Technical Report CECS-02-13, April 12, 2002. Center for Embedded Computer Systems University of California, Irvine Irvine.
[4] J. S. Sun and R. W. Brodersen. “ Design of System Interface Modules ”. In Proceedings of International Conference on Computer Aided Design, 1992.
[5] J. Akella and K. McMillan. “ Synthesizing converters between finite state protocols “. In Proceedings of the International Conference on Computer Design. Cambridge, MA, 1991.
[6] Sanjiv Narayan and Daniel D. Gajski. “ Interfacing Incompatible Protocols using Interface Process Generation. Proceeding of 32nd ACM/IEEE Design Automation Conference.1995.
[7] Jan Madsen and Bjarne Halk. “An Approach to Interface Synthesis.” Proceedings of the 8th International Symposium on System synthesis. 1995.
[8] V. D’silva, S.Ramesh and Arcot Sowmya. “ Bridge Over Trobled Wrappers : Automated Interface Synthesis”. Proceeding of the 17th international conference on VLSI Design. IEEEE. 2004
[9] G. Borriello and R. H. Katz. “ Synthesis and Optimization of Interface Transducer Logic “. Proceedings of the international Conference on Computer Aided Design, 1987.
[10] Vijay K. Madisetti and Lan Shen. “ Interface Design for Core-Based Systems” IEEE Design & Test of Computers. 1997.
[11] Roman L. Lysecky, Frank Vahid, Tony D. Givargis. “ Techniques for Reducing Read Latency of Core Bus Wrappers.” Proceedings of the conference on Design, automation and test in Europe. DATE, 2000.
[12] Kenichiro Anjo, Atsushi Okamura, and Masato Motomura. “ Wrapper-Based Bus Implementation Techniques for Performance Improvement and Cost Reduction.” Custom LSI Div., NEC Electron. Corp., Kanagawa, Japan; Solid-State Circuits, IEEE Journal
[13] Roman Lysecky and Frank Vahid. “Prefetching for Improved Bus Wrapper Performance in Cores”. ACM Transactions on Design Automation of Electronic System. 2002.
[14] Ilkka Saastamoinen, David Siguenz-Tortosa, and Jari Nurmi. “ Interconnect IP Node for Future System-onChip Designs” Proceedings of 1st International Workshop on Electronic Design, Test and Applications, IEEE, DELTA, 2002.
[15] Carloni, L.P. Sangiovanni-Vincentelli, A.L. “Coping with latency in SOC design” California Univ., Berkeley, CA; Micro, IEEE.2002.
[16] D. Panigrahi, C.N. Taylor, S. Dey. “Interface based hardware/software validation of a system-on-chip” IEEE International High-Level Validation and Test Workshop (HLDVT'00)
[17] W. Cesário,A. Baghdadi, L. Gauthier ,D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, M. Diaz-Nava. “Component-based design approach for multicore SoCs” Proceedings of the 39th conference on Design automation. ACM. 2002.
[18] Praveen Bhojwani and Rabi Mahapatra. “Interface Cores with On-Chip Packet-Switched Networks.” Proceedings of the 16th International Conference on VLSI Design, 2003.
[19] N. Swaminathan, “Communication Synthesis for On-Chip Networks”, Master Thesis, Texas A&M University, 2002.
[20] Erik J. Marinissen, Sandeep k. Goel, and Maruice Lousberg. “Wrapper Design for Embedded Core Test” Proceedings International Test Conference 2000.
[21] Kurt Keutzer, sharad Malik, A. Richard Newton, Jan M. Rabaey, and A. Sangiovanni-Vincentelli. “ System-Level Design: Orthogonalization of Concerns and Platform-Based Design” IEEE Transactions on Computer-Adied Design of Integrated Circuits and Systems. 2000.
[22] On-Chip Bus Development Working Group. “Virtual Component Interface Standard Version 2”, April 2001.
[23] “AMBATM Specification Revision 2.0”, May 13,1999.
[24] PCI Special Interest Group, “PCI Local Bus Specification Revision 2.2” December 18, 1998.
[25] “IP Qualification Guidelines” STC. Industrial Technology Research Institute. 2003.

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