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系統識別號 U0026-0812200910213348
論文名稱(中文) 階層式介面電路設計方法:以即時MP3編解碼系統為例
論文名稱(英文) Hierarchical Interface Design Methodology: Using Real-Time MPEG1 Audio layer3 codec as a case
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 90
學期 2
出版年 91
研究生(中文) 鄭君聖
研究生(英文) Jun-Sheng Zheng
電子信箱 echoiii@j92a21.ee.ncku.edu.tw
學號 n2689181
學位類別 碩士
語文別 英文
論文頁數 99頁
口試委員 指導教授-周哲民
口試委員-鄺獻榮
口試委員-陳培殷
口試委員-戴顯權
中文關鍵字 介面電路  介面設計 
英文關鍵字 interface  interface design  VCI  MP3 
學科別分類
中文摘要 在本論文中,一個可快速設計單晶片之介面電路,名為階層式電路設計方法和其模型被提出,此方法可被使用於快速並簡單的整合各種具有不同介面之矽智產。其主要的概念為其將矽智產本身模組和其介面分開設計,並導入一虛擬介面的概念,將所有具虛擬介面之矽智產模組視為一虛擬元件,如此這些虛疑元件將有一共同且簡易的虛疑介面元件協定而能輕易的和各種不同的系統匯流排進行整合。為了驗證其實際之可行性,我們使用此階層式介面電路設計方法來實現一即時MP3編解碼系統之介面。在此即時MP3編解碼系統中,我們使用了化簡過後的演算法,和管線化的架構來實現其中需要高計算複雜度的部份,如多相分析或合成濾波器,修改過的離散餘弦轉換或反離散餘弦轉換。最後我們使用軟硬體共同模擬的方法來驗証整個即時MP3編解碼系統。經由實驗的結果可以看到階層式介面電路設計方法對於整個系統的影響並不大,因此藉由此方法我們可以輕易整合各個不同的矽智產進而減少上市時間。
英文摘要 In this thesis a method for rapidly SoC IP interface design, which is called hierarchical interface design method and models is presented. The hierarchical interface design method is an interface design scheme that can be used to integrate different IPs easily. The main concept is to design IP and its interface separately. It introduces a virtual interface concept and views every IP as a virtual component. Since every virtual component has a simple and fixed virtual component interface protocol, they can be integrated into any bus architecture easily. To verify the practicability, we use the hierarchical interface design method to implement a real-time MP3 codec system interface. We use a simplified algorithm and pipelined architecture to perform high computation complexity part (poly phase analysis/synthesis filter bank, MDCT/IMDCT) of MP3 coding/decoding process. Finally a software/hardware co-simulation is done to verify the entire MP3 real-time codec system. Experiments show that the hierarchical interface design methodology results in minor hardware overhead on the original design. Different IPs can integrate in this scheme to reduce time to market.
論文目次 Chinese abstract
English abstract
Chapter 1 Introduction
1-1 Introduction to MPEG Audio Layer III 1
1-2 Introduction to Interface Design 2
1-3 Introduction to Hierarchical Interface Design Model 3
1-4 Summary 4
Chapter 2 Hierarchical Interface Design Model and Method
2-1 Introduction to Hierarchical Interface Design Method 5
2-2 Definition of Data 6
2-3 Hierarchical Description of Interface Circuit 7
2-3-1 Application Level 7
2-3-2 Functional Level 8
2-3-3 Virtual Component Level 8
2-3-4 State Transition Level 10
2-4 Classifications of Interface Design 11
2-5 Hierarchical Interface Design Model 12
2-5-1 Abstract Interface Design Model 13
2-5-2 Virtual Component Interface Design Model 15
2-5-3 State Based Interface Design Model 16
2-6 Hierarchical Interface Design Method 20
2-7 Peripheral Virtual Component Interface (PVCI) 23
Chapter 3 MPEG1 Audio Layer III Encoding
3-1 Introduction to MPEG Audio Layer III Encoding 30
3-2 Auditory Masking Effect and Psychoacoustic model 31
3-3 Poly Phase Analysis Filter Bank 32
3-4 MDCT 33
3-5 Reordering 35
3-6 Alias Reduction 36
3-7 Scalefactor Selection information (scfsi) Calculation 36
3-7 Nonuniform Quantization 38
3-8 Huffman coding 38
Chapter 4 MPEG1 Audio Layer III Decoding
4-1 Introduction to MPEG Audio Layer III Decoding 40
4-2 Synchronization and CRC check 41
4-3 Side information 42
4-4 Scalefactor decoder 43
4-5 Huffman decoder 45
4-6 Invert Quantization 47
4-7 Reordering & Alias Reduction 47
4-8 Stereo Processing 48
4-9 IMDCT 49
4-10 Poly Phase Synthesis filter bank 51
Chapter 5 MP3 Encoder Analysis and Design
5-1 Analysis of Encoder Complexity 53
5-2 Algorithm Simplification of Subband and MDCT 54
5-3 Implementation of Poly Phase Analysis Filter Bank 57
5-4 Implementation of MDCT 60
5-5 Interface Design of Encoder 63
5-5-1 Application level analysis 63
5-5-2 Functional level analysis 64
5-5-3 Virtual Component level analysis 65
5-5-4 State transition level analysis and implementation 67
5-5-5 Wrapper Design 69
Chapter 6 MP3 Decoder Analysis and Design
6-1 Analysis of Decoder Complexity 72
6-2 Algorithm Simplification of IMDCT and Subband 73
6-3 Implementation of IMDCT 75
6-4 Implementation of Poly Phase Synthesis Filter Bank 77
6-5 Interface Design of Decoder 80
6-5-1 Application level analysis 80
6-5-2 Functional level analysis 81
6-5-3 Virtual Component level analysis 83
6-5-4 State transition level analysis and implementation 85
Chapter 7 Synthesis Result and Verification
7-1 Timing Simulation of Encoder 89
7-2 Synthesis Result of Encoder 90
7-3 Timing Simulation of Decoder 91
7-4 Synthesis Result of Encoder 92
7-5 Verification Strategy 93
Chapter 8 Conclusion
8-1 Conclusion 96
Reference 97
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