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系統識別號 U0026-0712201516490200
論文名稱(中文) 新穎熱燈絲沉積系統製作CMOS電晶體元件
論文名稱(英文) CMOS Devices Developed by Novel Hot Wire Implantation Doping Technology
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 104
學期 1
出版年 105
研究生(中文) 吳政儒
研究生(英文) Cheng-Ju Wu
學號 Q16024163
學位類別 碩士
語文別 英文
論文頁數 85頁
口試委員 指導教授-張守進
口試委員-陳志方
口試委員-李清庭
口試委員-閔庭輝
口試委員-林建德
中文關鍵字 熱燈絲  摻雜  互補式金氧半場效電晶體 
英文關鍵字 Hot Wire  Doping Technology  CMOS 
學科別分類
中文摘要 金氧半場效電晶體 (MOSFET) 尺寸逐年縮小, 將在傳統的矽基板電晶體將面臨嚴重的物理限制, 例如短通道效應。因此許多研究致力於解決短通道效應, 例如: FinFet、3D-IC 或是High K 材料。其中淺接面摻雜技術也是其解決短通道效應的方法之一。 若可以在MOSFET 的通道裡形成奈米級的摻雜深度並且降低摻雜製程中對矽晶格的破壞將可以大幅降低短通道效應。由許多文獻指出本篇論文使用的熱燈絲沉積系統是一種摻雜技術可以達到淺接面的摻雜深度並且達到對矽基板少量的摻雜破壞。
在此論文中以電漿輔助熱燈絲沉積系統製作N和P型的金氧半場效電晶體並探討不同燈絲溫度對電晶體有何電性的影響。本論文也將以HWCVD製作在SOI基板之MOSFET並探討漏電流效應。研究中發現越高的燈絲線溫將會影響臨界電壓以及次臨界擺幅, 藉由這兩種數據結果得出越高的線溫可以到達越深的摻雜深度。本篇論文N型和P型之MOSFET的最佳線溫為1800℃以及 1650℃, 此溫度下有較佳的次臨界擺幅與較低的漏電流。最終透過此製成方法成功將N和PMOSFET結合成互補式金氧半場效電晶體 (CMOS)。
英文摘要 As the MOSFET devices have been scaling down, short channel effects become serious problems for traditional bulk MOSFETs. As the result, alternative MOSFET structure has been proposed. Shallow doping profiles is a solution. Shallow doping profiles in drain and source and reducing implantation damage are the most popular methods to suppress short channel effect. In lots of research, HWCVD doping system was a choice we applied to reach the object
In this thesis, the P and N MOSFET devices on bulk-Si with HWCVD assistant ICP doping system were investigated and the characteristic and the reliability of device with various dopant wire temperature were discussed. Silicon-on-insulator was used to test reliability in this work. It is observed that the drain current, threshold voltage and off-state leakage current would be affected due to the difference of doping depth. The n-MOSFET and p-MOSFET device with 1800℃and 1650℃ catalysts temperature has batter characteristic such as lower leakage current and subthreshold swing. Eventually, we combined the p and n MOSFET to fabricate a Complementary Metal-Oxide-Semiconductor (CMOS) device.
論文目次 摘要 I
Abstract III
誌謝 V
Content 1
Table Caption 5
Figure Caption 6
Chapter 1 Introduction 10
1.1. Background and Motivation 10
1.2. Present doping techniques 12
Reference 21
Chapter 2 Fabrication System and Important Parameters 26
2.1 Fabrication System 26
2.1.1 RCA clean System 26
2.1.2 Furnace Tube System 27
2.1.3 RF Sputtering System 28
2.1.4 Mask Aligner 29
2.1.5 Hot Wire Chemical Vapor Deposition 30
2.1.6 Rapid Thermal Annealing 32
2.2 Introduction of Analysis Equipment 33
2.2.1 Auger Electron Spectroscopy (AES) 33
2.2.2 Transmission Electron Microscopy (TEM) 34
2.2.3 Microscopes Raman Spectrometer 34
2.2.4 Energy Dispersive X-ray Spectroscopy (EDX) 35
2.3.5 Secondary Ion Mass Spectrometry 36
2.3 Important Parameters 37
2.3.1 Field-Effect Mobility 37
2.3.2 Threshold Voltage (VT) 38
2.3.3 Gate Electrode Work Function 38
2.3.4 On/off current Ratio (Ion/off) 39
2.3.5 Subthreshold Swing (S.S) 39
Reference 44
Chapter 3 Experimental Methods and Process in MOSFET 46
3.1 Experiment Procedure 46
3.2 Experiment Process steps 47
3.2.1 RCA Clean Wafers 47
3.2.2 Silicon Etching 47
3.2.3 Dry Oxide 48
3.2.4 Photo lithography 48
3.2.5 RF Sputter 49
3.2.6 ICP Etching SiO2 49
3.2.8 Hot Wire Chemical Vapor Deposition 49
3.2.8 Rapid Thermal Annealing 50
3.2.9 Source/Drain electrode 50
Chapter 4 Results and Discussion 59
4.1 Phosphorus- Doping Analysis 59
4.2 N-MOSFET Electrical Characteristics 60
4.2.1 Threshold Voltage via Wire Temperature 60
4.2.2 Subthreshold Swing via Wire Temperature 61
4.2.3 ION/IOFF 63
4.2.4 n-MOSFET on SOI Substrate 65
4.3 Boron - Doping Analysis 66
4.4 P-MOSFET Electrical Characteristics 67
4.5 CMOS Electrical Characteristics 67
Reference 82
Chapter 5 Conclusion and Future work 84
5.1 Conclusion 84
5.2 Future Work 85
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