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系統識別號 U0026-0708201809545500
論文名稱(中文) 實現於NetFPGA SUME之低延遲權證交易風險管控方法
論文名稱(英文) A Low-Latency Warrants Trading Scheme of Risk Management Using NetFPGA SUME
校院名稱 成功大學
系所名稱(中) 資訊工程學系
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 106
學期 2
出版年 107
研究生(中文) 王偉立
研究生(英文) Wei-Li Wang
學號 P76054143
學位類別 碩士
語文別 英文
論文頁數 54頁
口試委員 指導教授-張燕光
口試委員-王丕中
口試委員-陳永源
口試委員-許靜芳
口試委員-賴裕昆
中文關鍵字 高頻交易  NetFGPA SUME 
英文關鍵字 High frequency trading (HFT)  NetFPGA SUME 
學科別分類
中文摘要 隨著科技的發展,在股票市場中電子交易平台已十分普及。透過電子交易,投資人可以便利又快速地透過網路或特定軟體進行股票的下單交易。相對於傳統透過電話或是至交易所親自辦理的方式,電子交易平台[1][2]提供有效率且更快速的交易模式。在這種新的交易方式下,有人提出了高頻交易 (High Frequency Trading)[3][4]的技術。高頻交易主要利用自動化的交易程式,搭配高速、高效能的設備與網路,透過節省交易訊息傳輸、策略判斷的時間延遲來達到賺取股票買賣的價差的目的。
在權證市場中,也可以看到高頻交易的應用。券商為了增進權證市場流動性,會透過自動化的軟體程式進行造市[5][6]的行為,並期望其延遲越低越好。造市是券商利用自己的帳戶進行短線的買賣動作,以達到活絡此項商品/引投資人前來交易的目的。對造市者來說,風險管控是很重要的一環。造市的過程中必須持續不斷的接收最新的即時市場行情,並且必須隨時準備刪除已經送出的委託訂單,避免因為失去權證的最大持有占比導致大量的虧損。
基於上述的理由,我們提出了硬體風險管控處理平台,並將此平台實現於NetFPGA SUME開發版[7]上。我們設計的系統可以在1µs內解碼市場行情、產生對應的刪單請求封包,並送至證交所,因此證券商可以透過我們提出的系統來確保持有所發行的證券的最大比例。另外,我們設計了兩個方案來取得查詢延遲與資源使用之間的權衡。
英文摘要 As the communication technology advances, electronic stock trading become more widespread in stock market. Market participants can use network to issue the stock orders rapidly and conveniently. Traditionally people make the stock order by making a phone call or going to stock exchange in person. Electronic stock trading[1][2] is more efficient and convenient. Because of this new electronic stock trading, the electronic trading technology called High Frequency Trading(HFT)[3][4] is proposed. The main idea of HFT is to reduce the cost of the transmission time and the strategy compute time to earn the price difference in stock trading. In order to achieve this goal, they use automated trading software with high speed network and high efficiency network device.
There are also some applications about HFT in the warrants market. In order to make warrants market more active, the broker will do “market making” by automated software, and want to reduce the latency. Market making is an action launched by broker. The goal of market making[5][6] is to activate the warrants market by using broker’s accounts to buy or sell the warrants, for attracting more market participants to join the market. For broker, “risk management” is important. The brokers should receive lots of latest market data and send “cancel request” of the sent order at any time to prevent the large financial loss caused by losing the maximum shareholding.
In this paper, we proposed a hardware risk management system based on NetFPGA SUME[7]. Our system can decode the market information, format the corresponding cancel request and send the formatted packet to stock exchange in 1µs. So that the brokers can assure the maximum holding ratio of the issued warrants by the proposed system. Also, we design two scheme to make a trade-off between lookup latency and resource utilization.
論文目次 摘要 I
ABSTRACT II
誌謝 III
TABLE OF CONTENTS IV
LIST OF TABLES VI
LIST OF FIGURES VII
CHAPTER 1 INTRODUCTION 1
1.1 ELECTRONIC TRADING OF STOCK MARKET 1
1.1.1 Market Maker 1
1.1.2 Risk management of Electronic Trading System 2
1.2 DATA TRANSMISSION PROTOCOL OF TAIWAN STOCK EXCHANGE 3
1.2.1 IP Feed Market Information 3
1.2.2 FIX 4.4 Protocol 5
1.3 NETFPGA SUME 7
CHAPTER 2 RELATED WORK 9
2.1 REFERENCE PROJECTS ON NETFPGA SUME 9
2.2 SOFTWARE-BASED TRADING PROCESSOR 10
2.3 LOW-LATENCY FPGA-BASED TRADING PROCESSOR 11
2.4 HASHING DESIGN ON FPGA 12
2.4.1 Cuckoo Hashing 13
2.4.2 One-at-a-time hash function 15
CHAPTER 3 PROPOSED DESIGN AND IMPLEMENTATION 16
3.1 SYSTEM OVERVIEW 16
3.1.1 Inter-Module Communication 19
3.2 IMPLEMENTATION 22
3.2.1 User Data Path 22
3.2.2 IP Feed / FIX Order Parser 23
3.2.3 Register Infrastructure 26
3.2.4 FIX Generator 27
3.2.4.1 Stock_ID_Mapping Submodule 29
3.2.4.2 Warrant_ID_Mapping Submodule 33
3.2.4.3 Order_ID_Mapping Submodule 38
3.2.4.4 FIX_Formatter 43
CHAPTER 4 EXPERIMENTAL RESULTS 44
4.1 EXPERIMENT ENVIRONMENT 44
4.2 EXPERIMENTAL RESULTS AND ANALYSIS 48
CHAPTER 5 CONCLUSION 52
REFERENCE 53
參考文獻 [1] M.J. Barclay, T. Hendershott, and D.T. McCormick. “Competition among trading venues: Information and trading on electronic communications networks.” The Journal of Finance 58, 2637-2665, 2003.
[2] 台灣證券交易所。 電子交易簡介。
http://www.twse.com.tw/ch/products/publication/download/0001000042.htm
[3] M. Chlistalla, “High-frequency trading Better than its reputation?.” Deutsche Bank research report, 2011.
[4] B Biais, “High frequency trading” Manuscript, Toulouse University, IDEI, 2011
[5] Y Simaan, “Market maker quotation behavior and pretrade transparency”, Journal of Finance 58, 1247-1267, 2003
[6] Y Amihud, “Dealership market: Market-making with inventory”, Journal of Financial Economics 8, 311-353, 1980
[7] NetFPGA Organization, “NetFPGA SUME Public”.
https://github.com/NetFPGA/NetFPGA-SUME-public/wiki
[8] 台灣證券交易所電腦規劃部。NEW FIX 4.4電文規範。
http://www.twse.com.tw/zh/brokerService/brokerServiceComputer
[9] 台灣證券交易所電腦規劃部。台灣證券證交所資訊傳輸作業手冊。版 本 B.11.08。http://www.twse.com.tw/zh/brokerService/brokerServiceComputer
[10] NetFPGA Organization, “NetFPGA 1G CML”. https://github.com/NetFPGA/NetFPGA-public/wiki/Home_NetFPGA-1G-CML
[11] NetFPGA Organization, “NetFPGA SUME Reference NIC”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-NIC
[12] NetFPGA Organization, “NetFPGA SUME Reference Learning Switch”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-Learning-Switch
[13] NetFPGA Organization, “NetFPGA SUME Reference Router”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-Router
[14] Xilinx, “AXI4-LITE IP Interface document”.
https://www.xilinx.com/products/intellectual-property/axi_lite_ipif.html#documentation
[15] NetFPGA Organization, “NetFPGA SUME Blueswitch Contrib Project”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Blueswitch---Contrib-Project
[16] NetFPGA Organization, “NetFPGA SUME Reference NIC Nfmac10g”. https://github.com/forconesi/nfmac10g#nfmac10g-open-source-10gbe-mac-for-fpgas
[17] QuickFIX Open Source http://www.quickfixengine.org/
[18] C Leber, “High Frequency Trading Acceleration using FPGAs”, 2011 21st International Conference on Field Programmable Logic and Applications, 317-322
[19] Mellanox technologies Solution Brief, 2015,
http://www.mellanox.com/related-docs/applications/SB_HighFreq_Trading.pdf
[20] FAST protocol specification
http://ftp.moex.com/pub/FAST/Spectra/test/spectra_fastgate_en.pdf
[21] R Pottathuparambil, “Low-latency FPGA Based Financial Data Feed Handler”,
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 93-96
[22] A Boutros, “Build Fast, Trade Fast: FPGA-based High-Frequency Trading using High-Level Synthesis”, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1-6
[23] Xilinx, “Vivado High-Level Synthesis”.
https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
[24] R Pagh, “Cuckoo Hashing”, Journal of Algorithms 51, 122-144, 2004
[25] B. Jenkins, http://burtleburtle.net/bob/hash/doobs.html
[26] Xilinx, “AXI Interconnect”.
https://www.xilinx.com/products/intellectual-property/axi_interconnect.html
[27] N. Zilberman, NetFPGA SUME Tutorial Slide, Unervisity of Cambridge. http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/workshop/fpl-august-2015/material/slides/2015_FPL_tutorial.pdf
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