||Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node
||MS Degree Program on Nano-Integrated Circuit Engineering
self-aligned silicon nanowire FETs
The evolution of semiconductor technology has been progressed since Moore’s Law proposed in 1964. Dimension scaling is always the challenge for each technology node to reduce producing cost. With the continuous scaling of devices, short-channel effects are more and more severe in limiting the performance enhancement. Multi-gate struc-tures, which enhance the gate control on short-channel effects and optimize the electri-cal characteristics, can overcome the limitation; FinFET is generally applied for ad-vanced semiconductor fabrications. However, for sub-5 nm technology node, FinFETs can not offer the enough gate control, resulting in worse short-channel effects. On the other hand, GAA MOSFETs with the superior gate control of channel electrostatic are considered as a possible extension for the following technology nodes. Nevertheless, they increase the undesirable parasitic capacitances.
In this thesis, an analytical model is used to calculate the parasitic capacitances caused by GAA MOSFETs. Next, the optimization by inner spacer is presented to re-duce the additional parasitic capacitances. Such methodology helps us to ensure that the improvement is effective and feasible.
Then we use Synopsys TCAD to do the process simulations. GAA MOSFETs are processed with SiGe epitaxy. Electrical characteristic comparison for the devices with and without inner spacers is discussed.
5nm technology node in ITRS roadmap is the specification we adopt in this thesis. Different spacer lengths are the main topic; the longer spacers extend the effective channel length and improve short-channel effects.
Furthermore, the future design, a new integration scheme featuring bulk Si-base and cost-effective fabrication, is proposed. To overcome the drawback of GAA MOSFETs compared to FinFET: the increase of parasitic capacitances, inner spacers are adopted in fabrication. The proposed process is feasible and promising in the future based on our preliminary data.
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CHAPTER 1 INTRODUCTION 1
1-1 Background and Motivation 1
1-2 Multi-gate MOSFETs 3
1-2.1 FinFET 3
1-2.2 Gate-all-around (GAA) MOSFETs 4
1-3 Simulation tool introduction 5
1-4 Overview of the thesis 6
CHAPTER 2 PARASITIC CAPACITANCE ANALYTICAL MODEL FOR MULTI-GATE MOSFETS 7
2-1 Capacitance modeling methodology 7
2-2 FinFET versus conventional GAA MOSFET at 5nm technology node 9
2-3 Parasitic capacitance of GAA MOSFETs with inner spacers 11
CHAPTER 3 EVOLUTION OF GAA MOSFETS WITH INNER SPACERS AT 5 NM TECHNOLOGY NODE 15
3-1 Device Fabrication 15
3-2 Electrical characteristics 17
3-3 Comparison of the devices with and without inner spacers 22
3-4 Time Delay 26
3-5 Performance optimization 29
CHAPTER 4 PROPOSED PROCESS FOR THE FUTURE DESIGN 33
4-1 Cost-effective, self-aligned, and bulk Si-based GAA MOSFETs 33
4-2 Stacked-nanowire formation 36
CHAPTER 5 CONCLUSION 38
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