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系統識別號 U0026-0702201813575800
論文名稱(中文) 利用內部側壁絕緣層製程改善及優化環繞式閘極電晶體特性
論文名稱(英文) Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node
校院名稱 成功大學
系所名稱(中) 奈米積體電路工程碩士學位學程
系所名稱(英) MS Degree Program on Nano-Integrated Circuit Engineering
學年度 106
學期 1
出版年 107
研究生(中文) 陳仕豪
研究生(英文) Shi-Hao Chen
學號 Q76054110
學位類別 碩士
語文別 英文
論文頁數 42頁
口試委員 指導教授-江孟學
口試委員-高國興
口試委員-陳志方
口試委員-許渭州
口試委員-盧達生
中文關鍵字 奈米線電晶體  環繞式閘極電晶體  自我對齊矽奈米線電晶體  寄生電容  半導體工藝模擬 
英文關鍵字 nanowire transistor  gate-all-around MOSFET  self-aligned silicon nanowire FETs  parasitic capacitance  TCAD simulation 
學科別分類
中文摘要 自1964年摩爾定律問世,半導體製程便不斷地進步。為了降低生產成本的尺寸微縮一直是每個節點的技術挑戰。電晶體微縮過程中短通道效應越顯嚴重,使用多閘極結構可以增加閘極控制能力、改善短通道效應、優化電晶體特性。而在鰭式場效應電晶體為目前廣泛應用之多閘極元件,然而在五奈米節點之下,三個方向的閘極通道包覆開始不能支撐及克服微縮所遇之短通道效應,而閘極控制能力更優越的環繞式閘極電晶體則被認為是下一世代的元件結構設計。然而其相對於鰭式場效應電晶體卻造成了更多的寄生電容效應。
在本篇論文中,我們利用電容計算模型去估算環繞式閘極電晶體造成之非預期寄生電容大小,並提出藉由增加內部側壁絕緣層的製程,以降低額外寄生電容,藉由模型計算我們能夠確定這樣的製程方向是有效且可行的。
接著我們利用半導體工藝模擬工具進行實際製程的模擬,我們以矽鍺磊晶的方式製成環繞式閘極電晶體,並比較具內部側壁絕緣層及不具內部側壁絕緣層的結構其電流特性差異,優劣等。
在論文中我們以國際半導體技術發展路線圖(ITRS)提供的五奈米節點尺寸為基準,針對不同的側壁絕緣層厚度進行探討,越厚的側壁絕緣層造成有效通道長度的增加並間接降低短通道效應的影響。
此外,論文中也提出了未來可行的研究方向應用,將具成本優勢的矽基底之環繞式閘極電晶體引入此次研究所發表之內部側壁絕緣層製程,能夠克服相較於鰭式場效應電晶體的劣勢:成本提升、寄生電容增加,在接下來的半導體製程世代中,會是具有前景且可行的電晶體結構。
英文摘要 The evolution of semiconductor technology has been progressed since Moore’s Law proposed in 1964. Dimension scaling is always the challenge for each technology node to reduce producing cost. With the continuous scaling of devices, short-channel effects are more and more severe in limiting the performance enhancement. Multi-gate struc-tures, which enhance the gate control on short-channel effects and optimize the electri-cal characteristics, can overcome the limitation; FinFET is generally applied for ad-vanced semiconductor fabrications. However, for sub-5 nm technology node, FinFETs can not offer the enough gate control, resulting in worse short-channel effects. On the other hand, GAA MOSFETs with the superior gate control of channel electrostatic are considered as a possible extension for the following technology nodes. Nevertheless, they increase the undesirable parasitic capacitances.
In this thesis, an analytical model is used to calculate the parasitic capacitances caused by GAA MOSFETs. Next, the optimization by inner spacer is presented to re-duce the additional parasitic capacitances. Such methodology helps us to ensure that the improvement is effective and feasible.
Then we use Synopsys TCAD to do the process simulations. GAA MOSFETs are processed with SiGe epitaxy. Electrical characteristic comparison for the devices with and without inner spacers is discussed.
5nm technology node in ITRS roadmap is the specification we adopt in this thesis. Different spacer lengths are the main topic; the longer spacers extend the effective channel length and improve short-channel effects.
Furthermore, the future design, a new integration scheme featuring bulk Si-base and cost-effective fabrication, is proposed. To overcome the drawback of GAA MOSFETs compared to FinFET: the increase of parasitic capacitances, inner spacers are adopted in fabrication. The proposed process is feasible and promising in the future based on our preliminary data.
論文目次 摘要 II
Abstract IV
Table Captions III
Figure Captions IV
CHAPTER 1 INTRODUCTION 1
1-1 Background and Motivation 1
1-2 Multi-gate MOSFETs 3
1-2.1 FinFET 3
1-2.2 Gate-all-around (GAA) MOSFETs 4
1-3 Simulation tool introduction 5
1-4 Overview of the thesis 6
CHAPTER 2 PARASITIC CAPACITANCE ANALYTICAL MODEL FOR MULTI-GATE MOSFETS 7
2-1 Capacitance modeling methodology 7
2-2 FinFET versus conventional GAA MOSFET at 5nm technology node 9
2-3 Parasitic capacitance of GAA MOSFETs with inner spacers 11
CHAPTER 3 EVOLUTION OF GAA MOSFETS WITH INNER SPACERS AT 5 NM TECHNOLOGY NODE 15
3-1 Device Fabrication 15
3-2 Electrical characteristics 17
3-3 Comparison of the devices with and without inner spacers 22
3-4 Time Delay 26
3-5 Performance optimization 29
CHAPTER 4 PROPOSED PROCESS FOR THE FUTURE DESIGN 33
4-1 Cost-effective, self-aligned, and bulk Si-based GAA MOSFETs 33
4-2 Stacked-nanowire formation 36
CHAPTER 5 CONCLUSION 38
References 40
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