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系統識別號 U0026-0609201811302200
論文名稱(中文) 一個操作在極低電壓下使用動態臨界電壓電晶體之低功耗十位元逐漸趨近式類比數位轉換器
論文名稱(英文) A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 106
學期 2
出版年 107
研究生(中文) 簡豪廷
研究生(英文) Hao-Ting Jian
電子信箱 dannie@sscas.ee.ncku.edu.tw
學號 N26034752
學位類別 碩士
語文別 英文
論文頁數 97頁
口試委員 指導教授-張順志
口試委員-謝志成
口試委員-許孟烈
口試委員-魏嘉玲
口試委員-蔡建泓
中文關鍵字 類比數位轉換器  逐漸趨近式  低功耗  低電壓  動態臨界電壓電晶體 
英文關鍵字 Analog-to-digital converter  Successive approximation register (SAR)  low power  low voltage  dynamic threshold voltage MOSFET (DT-MOS) 
學科別分類
中文摘要 隨著積體電路製程的發展,無線感測網路和攜帶式裝置逐漸被人們重視,為了延長這些裝置的使用壽命,節省能源的設計是必須的。而操作在低速度(≤1 MS/s)以及中高解析度(8~12 bits)的類比數位轉換器是感測系統中重要的電路,在許多類比數位轉換器架構中,低電壓逐漸趨近式類比數位轉換器有著較佳的能源轉換效率,所以非常地適合應用於無線感測裝置裡。然而在低電壓的操作下,產生了一些問題必需要去克服,像是漏電流、頻寬的限制以及雜訊的干擾等效應降低了類比數位轉換器的效能。
本篇論文所提出的逐漸趨近式類比數位轉換器使用了動態臨界電壓電晶體之技術,並提出一個高線性度、高頻寬、低漏電的取樣保持電路,直接有效地改善在低操作電壓下所遇到的問題,並且提升了整體類比數位轉換器的效能。除此之外,經由微調非同步時序,結合了動態臨界電壓電晶體以及可變重置時間之控制,優化了操作速度並且降低漏電的影響。
本設計以台積電40奈米CMOS標準1P9M製程實作晶片,其核心電路面積為0.0152 mm2。此晶片操作在0.3伏特電源供應及每秒十萬次的取樣頻率下,消耗功率為166.7 nW,其奈奎斯特輸入的有效位元為9.03位元;而操作在0.4伏特電源供應及每秒一百萬次的取樣頻率下,消耗功率則為796.4 nW,奈奎斯特輸入的有效位元為9.04位元,另外個別換算出的性能指標為3.19 fJ/conversion-step和1.51 fJ/conversion-step。
英文摘要 With the advancement of fabrication process, portable devices and wireless sensor networks are getting more popular. Energy-efficient design for these devices is necessary to prolong their lifetimes. In sensing systems, the ADC is one of the key building blocks, which requires moderate resolution (8-12 bits) and low sampling rate (100-1000 kS/s). Among various architectures, an ultra-low voltage successive-approximation-register (SAR) ADC has better energy efficiency and is suitable for these sensor systems. However, ultra-low voltage design induces some challenges we need to overcome, such as leakage current, limitation of bandwidth and noise degradation, which result in worse performance of an ADC.
In this thesis, we propose a high-linearity, high-bandwidth and low-leakage S/H circuit with the DT-MOS technique, which directly mitigates the above-mentioned problems of the S/H circuit and enhances the overall performance of the ADC at ultra-low voltage. In addition, an asynchronous timing scheme with the combination of DT-MOS and variable resetting timing control is implemented to optimize the operating speed of the SAR ADC and reduce the effect of leakage current.
The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology and the core area occupies 0.0152 mm2. At 0.3 V supply voltage and 100-kS/s, it consumes 166.7 nW and achieves 9.03 bits with Nyquist input. At 0.4 V supply voltage and 1-MS/s, it consumes 796.4 nW and achieves 9.04 bits with Nyquist input. The figure-of-merit (FoM) is 3.19 fJ/conversion-step and 1.51 fJ/conversion-step, respectively.
論文目次 Table of Contents VI
List of Tables VIII
List of Figures IX
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Chapter 2 Fundamentals of Analog-to-Digital Converters 5
2.1 Introduction 5
2.2 Analog-to-Digital Converter 5
2.3 Quantization Error 6
2.4 Resolution and Accuracy 9
2.5 Static Specifications 10
2.5.1 Offset Error 10
2.5.2 Gain Error 11
2.5.3 Nonlinearity 12
2.6 Dynamic Specifications 17
2.6.1 Signal-to-Noise Ratio (SNR) 17
2.6.2 Signal-to-Noise and Distortion Ratio (SNDR) 18
2.6.3 Effective Number of Bits (ENOB) 18
2.6.4 Spurious-Free Dynamic Range (SFDR) 19
2.6.5 Total Harmonic Distortion (THD) 20
2.6.6 Effective Resolution Bandwidth (ERBW) 21
2.6.7 Figure of Merit (FoM) 22
Chapter 3 Design Techniques of Low Power and Low Voltage SAR ADC 23
3.1 Introduction 23
3.2 Operation of the Conventional SAR ADC 24
3.3 The Switching Methods of Capacitor DAC 26
3.3.1 Conventional Switching Method 26
3.3.2 Split Capacitor Switching Method [13] 28
3.3.3 Monotonic Switching Method [4] 30
3.3.4 Vcm-based Switching Method [5] [6] 32
3.3.5 Summary 34
3.4 Techniques of Low Power and Low Voltage Design 36
3.4.1 Window Function in Binary Search Algorithm 36
3.4.2 Detect-and-Skip Algorithm 37
3.4.3 Flexible Comparator 38
3.4.4 Bi-directional Comparator 39
Chapter 4 Proposed 10-Bit Low Power SAR ADC at Ultra-Low Voltage 41
4.1 Introduction 41
4.2 Consideration of S/H circuit 43
4.2.1 Non-linearity Distortion and Leakage Distortion 43
4.2.2 Thermal Noise and Flicker Noise 46
4.3 Proposed Double-Bootstrapped Switch 46
4.4 Architecture of the Proposed SAR ADC 52
4.4.1 Splitting Monotonic Switching 53
4.4.2 Combination with Flexible Comparator and Non-binary Algorithm Compensation 55
4.5 Circuit-Level Design 57
4.5.1 Proposed Double-Bootstrapped DT-MOS Switch 57
4.5.2 Capacitive DAC 58
4.5.3 Dynamic Two-Stage Comparator 62
4.5.4 Proposed Asynchronous Timing Control 66
4.5.5 Simplified SAR Logic 68
4.5.6 Dynamic Latch 69
4.5.7 Digital Error Correction Decoder 72
Chapter 5 Simulation and Measurements Results 74
5.1 Introduction 74
5.2 Chip Floor Plan and Layout 74
5.3 Post-Layout Simulation Result 77
5.4 PCB Design 82
5.5 Die Micrograph and Measurement Setup 84
5.6 Measurement Results 86
Chapter 6 Conclusions and Future Work 92
Bibliography 94
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