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系統識別號 U0026-0605201316154600
論文名稱(中文) 快閃記憶體元件及周邊電路之可靠度研究
論文名稱(英文) Reliability Studies of Advanced NAND Flash Cells and Periphery Devices
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 101
學期 2
出版年 102
研究生(中文) 嚴進嶸
研究生(英文) Chin-Rung Yan
學號 Q18981167
學位類別 博士
語文別 英文
論文頁數 102頁
口試委員 指導教授-陳志方
口試委員-張守進
口試委員-方炎坤
口試委員-王水進
召集委員-金雅琴
口試委員-張鼎張
口試委員-葉文冠
口試委員-施文傑
口試委員-吳國銘
中文關鍵字 高壓元件LDMOS  熱載子可靠度  安全操作區間  崩潰電壓  快閃記憶體  介面狀態 
英文關鍵字 LDMOS  Hot carrier  Safe operating area  off-state breakdown  NAND Flash  interface states 
學科別分類
中文摘要 NAND Flash元件具有易積體化與高存取速度等優點,在智慧型手機當道的今日,其應用已成為行動產品的主力之一。本論文主要的目的為研究NAND Flash產品中所使用到的Periphery元件以及Cell元件之可靠度與元件特性。由於NAND Flash 產品中的cell元件在資料寫入或者抹除操作時需要高電壓20V之電源供給,而在讀取資料時又需要中低電壓,約10V以下不等,因此NAND Flash產品的Periphery 元件便需要依操作需求提供低、中和高三種範圍之電壓,而在本論文中的研究首先針對於用於高電壓操作的Periphery元件進行關於崩潰電壓與可靠度之研究探討,最後在討論NAND Flash Cell的可靠度分析。
由於提供給cell元件寫入資料時所用的高電壓會經過兩級,分別是位準轉移電路與字元線驅動電路,此兩電路皆使用LDMOS元件以耐25至30V之高偏壓。在第一級的位準轉移電路中的高壓元件為空乏型元件,高崩潰電壓為應用時的主要需求之一。實驗結果顯示該元件崩潰電壓的機制主要由GIDL和Junction Breakdown主導,並隨著漂移區域濃度的上升,崩潰電壓會呈現先上後下降的行為,可得一個優化的崩潰電壓實驗結果,其機制主要成因為電場較為均勻分佈,過濃和過淡的參雜會導致電場分別落於閘極邊緣和高濃度n+區以致崩潰電壓下降。此外,本研究也根據已建立的物理模型,成功地增加元件對製程變異性的容忍度。
在第二級的字元線驅動電路中,所使用的元高壓元件為增強型元件,本論文提出在漂移區的離子佈植製程之前,將犧牲氧化層由均勻的厚度改成漸進式的厚度,如此一來,離子佈植時將會看到不同的犧牲氧化層厚度,漂移區因此形成較為漸進式的接面,有效降低元件操作時的電場強度,進而改善了Kirk效應造成的基板電流、崩潰電壓、熱載子可靠度與元件的安全操作區域。
  論文的最後,主要探討NAND Flash Cell元件的interface state(NIT)的萃取,本研究成功地分別萃取出元件中間區域和角落區域之interface state並探討退化行為。因為NAND Flash特有的control gate recess之結構,此時分別量測cell處在寫入和抹除狀態時的Chare Pumping 電流會發現有所不同,由於在寫入狀態和抹除狀態分別有正的和負的臨界電壓與平帶電壓,因此control gate recess結構會影響沿著元件寬度方向的電子濃度,在寫入和抹除狀態有不同濃度分佈的進而影響Charge Pumping的結果。由模擬結果得到,cell在抹除狀態時,通道導通時電子反轉層因control gate加負的偏壓以致降低角落區域的電子濃度,此時角落區域將不貢獻charge pumping電流,而此時量測charge pumping電流由元件中間區域的NIT貢獻;反之在寫入狀態時,control gate的正偏壓雖然會讓角落區域電子濃度上升,但由於thermal emission的緣故,該靠近EC位置的NIT貢獻到charge pumping電流僅造成允許忽略之影響,此時可得元件全區域的NIT。最後再輔以3- Level Charge Pumping所得之NIT的密度能量分佈,各別萃取出位於元件角落和中間區域之NIT密度。研究的最後觀察NAND Flash元件在cycling後的退化行為,可發現到角落區域在stress後有較顯著的NIT之退化,其主因為角落通常有較高的電場所導致,退化由角落漸漸往中間區域延伸。
英文摘要 Recent years, NAND flash storage drive is one of the most important products used in smart mobile phone. The NAND Flash device is with the advantages which are high scalability and fast storage speed. The main purpose of this thesis is about the reliability studies of NAND Flash Cell and Periphery. Since the NAND flash needs high voltage around 20V during program / erase operation and median-low voltage around 10V during read operation, respectively, the periphery devices have to provide various kinds of voltages for NAND Flash operation. The first part research in this thesis focused on the studies of off-state breakdown and reliability of High-Voltage LDMOS Transistors. Finally, the reliability of NAND Flash Cell will be discussed in the final section.
The high voltage which is applied to NAND Flash Cell for Program/Erase operation is through 2 stages circuits. The first stage circuit is level-shift circuit and then word-line driver circuits. In level-shift circuit, one of the used devices is depletion-mode high-voltage LDMOS. For application, the high off-state breakdown (off-state BD) is one of the requirements for this device in level-shift circuit. In the experiments, we found that the off-state breakdown is dominated by gate-induced-drain-leakage (GIDL) and junction breakdown (BDj). The off-state BD increased with higher dosage of LDMOS N- drift region first and decreased finally, likes Bell-shape curve with an optimized point. The major mechanism of optimized point is caused by the uniform electric field (E-field) distribution. As the dosage of LDMOS N- drift region is with too heavy or slight may induce the E-field to close to gate edge or n+ portion, caused the off-state BD drop. Besides, in this work, we also based on the realized mechanism to find a method which is deeper implant make more margin for process variation.
The second stage is the word-line driver circuit which used enhanced-mode LDMOS. In this thesis, we proposed using gradual screen oxide replace uniform ones before the implant N- drift region of LDMOS. Thus, the implant process faces gradual screen oxide and induced gradual junction profile for N- drift region of LDMOS. The gradual junction profile effectively reduces the E-field for not only on-state but also off-state operation. The improvements include 2nd stage ISUB by Kirk Effect, off-state BD, hot carrier reliability and electrical safe-operating-area (E-SOA).
In the final section of this thesis, the extraction of interface state (Nit) had discussed for a NAND Flash Cell device. We successfully extracted and separated the Nit in corner region and center region of device in width direction, respectively. Since NAND Flash is with the structure of recess control gate, the charge pumping current (ICP) will be impacted by the data states like program and erase states. Because of the program and erase state are with positive and negative VTH/VFB, respectively. From the TCAD result, as the cell is erased, the density of electron inversion layer will be reduced by control gate with negative voltage. The ICP is contributed from center area and reflects the center Nit. On the other hand, control gate is biased positive voltage to monitor ICP in program state. Although the control gate with positive voltage causes higher electron density in the corner region, the thermal emission occurring neglects the impact to ICP. In program state, the charge pumping reflects the Nit of whole region. Besides, three level charge pumping method is used to monitor the Nit with energy distribution and support the extraction of Nit in center and corner region. Finally, the reliability of NAND Flash is discussed. Based on previous extraction results, experiment results show that the corner Nit is with worse degradation than center Nit due to higher corner E-field. The degradation extends from corner to center during stressing.
論文目次 Abstract ………………………………………………………………………………….ii
Chinese Abstract iv
Acknowledgements vi
Table of Contents viii
List of Tables x
List of Figures xi
List of Figures xi
Chapter 1
1.1 Memories 1
1.2 NAND Flash Device Introduction 3
1.3 Development of NAND Flash Device 4
1.4 Outline in this dissertation 5
References 15
Chapter 2
2.1 Basic Knowledge of NAND Flash 16
2.2 Tools for Experiment in this work –Equipment 19
2.3 Tools for Experiment in this work –Software 20
References 34
Chapter 3
3.1 Introduction 35
3.2 The application of used device in NAND Flash Product 37
3.3 Fabrication process and Device Structure of LDMOS 37
3.4 Monitor methods and parameters 38
3.5 Optimization of GIDL induced off-state Breakdown 39
3.6 Process Margin Improvement 43
3.7 Summary 45
References 59
Chapter 4
4.1 Introduction 60
4.2 The application of used device in NAND Flash Product 61
4.3 Fabrication process and Device Structure of LDMOS 62
4.4 Experiment Results and Discussions 63
4.5 Summary 66
References 74
Chapter 5
5.1 Introduction and Motivation 78
5.2 The device structures and experiments 79
5.3 Results and Discussions 81
5.4 Extraction Error Mention 87
5.5 Summary 88
References 97
Chapter 6
6.1 Summary 99
6.2 Future Work 101
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Ch.6
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