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系統識別號 U0026-0308201810045300
論文名稱(中文) 具高準確度低功耗及數位輸出之全新電壓型類比除法器
論文名稱(英文) Novel High-Accuracy Low-Power Voltage-Mode Analog Divider with Digital Output
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 106
學期 2
出版年 107
研究生(中文) 陳冠宏
研究生(英文) Kuan-Hung Chen
學號 N26050237
學位類別 碩士
語文別 英文
論文頁數 67頁
口試委員 指導教授-魏嘉玲
口試委員-張順志
口試委員-蔡建泓
口試委員-張簡樂仁
口試委員-許明華
中文關鍵字 電壓型除法器  類比除法器  高準確度除法器 
英文關鍵字 Voltage-mode divider  Analog divider  High-Accuracy divider 
學科別分類
中文摘要 作為四則運算之一,類比除法器至今已被用在許多的應用上。因除法器通常需要與其它電路做結合,與其它電路之相容性對一個除法器來說非常重要。因此,本論文提出一個全新架構之除法器,此除法器能實現兩個電壓之間的除法運算,且將結果直接轉為數位輸出。換句話說,此架構之除法器結合了一個類比除法器以及一個類比數位轉換器 (Analog-to-Digital Converter) 的功能。除此之外,此除法器更可以同時達到高準確度、低功耗以及不受製程變化影響的特性。
本晶片使用台灣積體電路公司0.35μm 2P4M混合訊號製程製作而成,晶片尺寸約為1.25×1.25mm2。本電路之除數輸入電壓範圍為0.1-1V,且被除數之輸入電壓範圍為0.1-1.5V。此外,此電路在3.3V之靜態功耗為205μW、最大功耗為440μW,且其最大誤差小於1.5%。
英文摘要 For being one of the four fundamental arithmetic operations, analog dividers have been utilized in many applications. Since the dividers are usually integrated with other circuits, it is important for dividers to be compatible with other circuits. Therefore, a novel architecture of analog divider is proposed in this thesis. The proposed divider can realize a dividing function of two voltage signals and directly convert the result into digital codes. In other words, it combines the functions of an analog divider and an analog-to-digital converter (ADC). Furthermore, it can achieve high accuracy, low power consumption, and be insensitive to process variation.
The proposed chip was fabricated by TSMC 0.35μm 2P4M CMOS/MEMS mixed-signal process, and the chip size is 1.25×1.25mm2. The input range of the dividend and the divisor is 0.1-1.5V and 0.1-1V, respectively. The maximal error of the proposed divider is lower than 1.5%. Moreover, the quiescent and maximal power consumption is 205μW and 440μW at 3.3V, respectively.
論文目次 Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 2
Chapter 2 Recent Researches of Analog Dividers 3
2.1 Recent Researches of Analog Dividers 3
2.1.1 Divider using a four quadrant multiplier and biasing control circuit 3
2.1.2 Current-mode multiplier/divider using the translinear method 6
2.1.3 Current-mode divider using the Geometric-Mean method 9
2.2 Summary of Recent Researches 12
Chapter 3 System Architecture and Circuit Design 13
3.1 Novel Architecture of Analog Divider 13
3.1.1 Voltage-mode divider using the Voltage-to-Time method 13
3.1.2 Alternative voltage-mode divider using the Voltage-to-Pulse method 16
3.2 Block Diagram 18
3.2.1 Voltage to Pulse Generator 19
3.2.2 Pulse Divider 27
3.2.3 Counter 32
3.2.4 Constant-gm bias circuit 33
3.3 Process Variation Sensitivity 34
Chapter 4 Simulation Result and Layout 38
4.1 Simulation Results 38
4.1.1 Pre-simulation results 38
4.1.2 Post-simulation results 42
4.2 Layout 46
4.3 Bonding Wire Diagram 47
Chapter 5 Measurement Result 48
5.1 Measurement Environment 48
5.2 Measurement Result 50
5.2.1 Measured waveform 50
5.2.2 Performance measurement 55
5.3 Measurement Result of Different Chips 60
5.4 Specification and Comparison 62
Chapter 6 Conclusion and Future Work 65
References 66
參考文獻 [1] Wen-Jui Wu, Chia-Ling Wei, “Design of an Impedance-to-Digital Converter for Electrochemical Impedance Spectroscopic Measurement System,” M.S. thesis, Dept. of Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R.O.C., Jun., 2013.
[2] Yi-Wen Wang, Chia-Ling Wei, “A Wide-Rang Programmable Sinusoidal Frequency Synthesizer for Electrochemical Impedance Spectroscopy Measurement System,” M.S. thesis, M.S. thesis, Dept. of Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R.O.C., Jul., 2012.
[3] Siang-Wei Wang, Chia-Ling Wei, “Design of Peak Detector and Divider for Electrochemical Impedance Spectroscopy Measurement System,” M.S. thesis, Dept. of Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R.O.C., Jan., 2017.
[4] Chia-Ling Wei, Yi-Wen Wang, and Bin-Da Liu, “Wide-Range Filter-Based Sinusoidal Wave Synthesizer for Electrochemical Impedance Spectroscopy Measurements,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 3, Sep. 2013, pp. 442-450.
[5] Tse-An Chen, Wen-Jui Wu, Chia-Ling Wei, and Bin-Da Liu, “Novel 10-Bit Impedance-to-Digital Converter for Electrochemical Impedance Spectroscopy Measurements,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 2, Apr. 2017, pp.370-379.
[6] Ivan Padilla-Cantoya, “Compact low-voltage CMOS analog divider using a four-quadrant multiplier and biasing control circuit,” in Proc. 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2012, pp.502–505.
[7] A.Mahmoudi, A.Mahmoudi, and KH.Hadidi, “A Novel Current-Mode Micropower Four Quadrant CMOS Analog Multiplier/Divider,” in Proc. 2007 IEEE Conference on Electron Devices and Solid-State Circuits (CEDSC), Dec. 2007, pp.321-324.
[8] Antonio J. Lopez-Martin, Carlos A. De La Cruz Blas, Jaime Ramirez-Angulo, and Ramon G. Carvajal, “Compact Low-Voltage CMOS Current-Mode Multiplier/Divider,” in Proc. Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May.-June. 2010, pp.1583-1586.
[9] Rodrigo Bispo dos Santos, Paloma M. S. Rocha Rizol, Leonardo Mesquita, “Design of CMOS Current-mode Multiplier-Divider circuit for type-2 FLC Applications,” in 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), Montevideo, Uruguay, Sep. 2015, pp. 1–4.
[10] Weihsing Liu, Shen-Iuan Liu, and Shui-Ken Wei, “CMOS Current-Mode Divider and Its Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, pp. 145-148, Mar. 2005.
[11] Texas Instruments, “Multiplier/Divider,” MPY100 datasheet, Sep. 2000.
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