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系統識別號 U0026-0307201818002400
論文名稱(中文) 相異製程之鰭式場效電晶體其可靠度之研究
論文名稱(英文) Analysis on Reliability for FinFET with Different Processes
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 106
學期 2
出版年 107
研究生(中文) 李佑軒
研究生(英文) Yu-Hsuan Lee
學號 Q16054029
學位類別 碩士
語文別 英文
論文頁數 74頁
口試委員 指導教授-陳志方
口試委員-張守進
口試委員-江孟學
口試委員-陳世志
口試委員-洪上超
中文關鍵字 鰭式場效電晶體  熱載子退化  負偏壓溫度不穩定性  氧化層預熱時間  磊晶製程距離 
英文關鍵字 FinFET  hot carrier effect  negative bias temperature instability  high K oxide preheat time  epitaxy proximity 
學科別分類
中文摘要 在本篇論文中,我們主要探討的元件為先進鰭式場效電晶體(Advanced-FinFETs),其中針對不同高介電常數(high K)氧化層的預熱時間(preheat time)與不同的磊晶製程距離(epitaxy proximity)對於基本電性、N型元件的熱載子可靠度與P型元件的負偏壓溫度不穩定性進行探討。在本篇論文裡,我們有三種不同高介電常數氧化層預熱時間的元件與三種不同磊晶製程距離的元件。
首先,說明此研究的動機並描述鰭式場效電晶體的結構、優缺點以及應用的領域,接著介紹熱載子效應與負偏壓溫度不穩定性的基本原理。
之後介紹本論文中的量測手法及偏壓條件的設定,並且說明可靠度評估的依據以及其電壓的設置。在元件基本電特性方面,我們將會呈現ID-VG、ID-VD以及IG-VG的量測結果。
量測的結果顯示相異氧化層預熱時間對於元件的基本電性沒有明顯的影響。在N型熱載子可靠度方面,元件的退化同時受到介面陷阱與氧化層缺陷影響,在P型負偏壓溫度不穩定性當中,則是由氧化層缺陷主導退化。不同氧化層預熱時間的電性退化趨勢與量值沒有明顯差異,退化的物理機制、缺陷位置與閘極品質也不會受到預熱時間的影響,因此我們推測預熱時間的長短並不會影響元件的電性與可靠度,只要有達到預熱的效果即可。
第二個部分分析不同磊晶製程距離,量測的結果顯示元件的基本電性沒有明顯的差異。在N型熱載子可靠度方面,元件的退化同時受到介面陷阱與氧化層缺陷影響,在P型負偏壓溫度不穩定性當中,則是由氧化層缺陷主導退化。不同磊晶製程距離的電性退化趨勢與量值沒有明顯差異,退化的物理機制與缺陷位置也不會受到磊晶製程距離的影響,因此我們推測是因為磊晶製程距離在晶圓上不同位置的差異過於微小大約只有埃(Å)等級,所以不會對元件的電性與可靠度造成影響。
英文摘要 In this thesis, we investigated devices is advanced-FinFETs, and analysis on different high K oxide preheat time and different epitaxy proximity for basic electrical characteristics, N-type device hot carrier reliability and p-type device negative bias temperature instability(NBTI). In our study, we have three devices with different high K oxide preheat time and three devices with different epitaxy proximity respectively.
First, we explained the motivation of this study and introduced the structure of FinFETs, its advantage and disadvantage, and it’s field of application. Moreover, hot carrier effect and NBTI physical mechanism were be introduced.
Then we introduced the measurement method and the setting of bias condition in this thesis, and explained the basis for reliability assessment and its voltage setting. We will present the measurement results for ID-VG, ID-VD and IG-VG in terms of the basic electrical characteristics of the FinFETs.
The measurement results show that the different oxide preheat time has no significant effect on the basic electrical properties of the device. In the reliability of the N-type hot carrier, the degradation of the device is affected by both the interface trap and the oxide layer defect. In the P-type negative bias temperature instability, the oxide layer defect dominates the degradation. There is no significant difference between the electrical degradation trend and magnitude of different high K oxide preheat time. The physical mechanism of degradation, defect location and gate quality will not be affected by the preheat time. Therefore, we speculate that the length of preheat time will not affect the electrical characteristics and reliability of devices, as long as they have the effect of preheating can be achieved.
The second part analyzed the different epitaxy proximity. The results of the measurements show that there is no significant difference in the basic electrical properties of the devices. In the reliability of the N-type hot carrier, the degradation of the device is affected by both the interface trap and the oxide layer defect. In the P-type negative bias temperature instability, the oxide layer defect dominates the degradation. There is no obvious difference between the electrical degradation trend and magnitude of different epitaxy proximity, and the physical mechanism and defect location will not be influenced by the epitaxy proximity. Therefore, we speculate that the difference of epitaxy proximity at different positions on the wafer is too small roughly only Angstrom (Å) level, so it will not affect the electrical and reliability of the devices.
論文目次 中文摘要 I
Abstract III
致謝 V
Content VI
Table Captions VIII
Figure Captions IX
Chapter1 Introduction 1
1-1 Motivation 1
1-2 Introduction of FinFET device and applications 3
1-3 Introduction of hot carrier reliability 4
1-4 Introduction of negative bias temperature instability reliability 5
1-5 About this thesis 7
Chapter 2 Device Characteristics and Measurement Setup 13
2-1 Introduction 13
2-2 Devices structure description 13
2-3 Measurement setup 14
2-3-1 Measurement setup 14
2-3-2 ID-VG measurement 14
2-3-3 ID-VD measurement 15
2-3-4 IG-VG measurement 15
2-4 Stress condition 16
2-4-1 Stress measurement setup 16
2-4-2 NMOS hot carrier stress 16
2-4-3 PMOS negative bias temperature instability stress 17
2-5 Summary 19
Chapter 3 Investigation of different high K preheat time 32
3-1 Introduction 32
3-2 Analysis of fresh device characteristic 33
3-3 Analysis of NMOS HCI reliability 33
3-4 Analysis of PMOS NBTI reliability 35
3-5 Summary 38
Chapter 4 Investigation of different epitaxy proximity 51
4-1 Introduction 51
4-2 Analysis of fresh device characteristic 52
4-3 Analysis of NMOS HCI reliability 52
4-4 Analysis of PMOS NBTI reliability 54
4-5 Summary 56
Chapter 5 Conclusion and Future Work 65
5-1 Conclusion 65
5-2 Future Work 66
Reference 67
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