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系統識別號 U0026-0208202017545200
論文名稱(中文) 實現可配置環震盪器及鄰近比較策略於FPGA的物理不可仿製功能
論文名稱(英文) Design and Implementation of Configurable RO and Adjacency-based Comparison for FPGA-based PUF
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 2
出版年 109
研究生(中文) 徐子翔
研究生(英文) Tzu-Hsiang Hsu
學號 N26054972
學位類別 碩士
語文別 英文
論文頁數 46頁
口試委員 指導教授-謝明得
口試委員-郭致宏
口試委員-黃稚存
口試委員-黃穎聰
中文關鍵字 環形震盪器  現場可程式化邏輯閘陣列  可配置延遲線  密鑰安全  物理不可複製函數 
英文關鍵字 Ring oscillator  FPGA  Programmable delay line  key security  PUF 
學科別分類
中文摘要 物理不可仿製功能(PUF)用於設備的身分驗證及密鑰生成,可在晶片上生成秘密資訊而不需要儲存關鍵資訊。其中環形震盪器(Ring Oscillaor)因其在現場可程式化邏輯閘陣列(FPGA)上易於實現而備受關注。但是基於結構上的不同以及區域性的潛在偏差,不是所有的挑戰與回應對(CRPs)都適合使用,而當我們選擇了高唯一性的回應後,由於操作環境變化又會導致其穩定性不好同時滿足。環震盪器基於鄰近比較且使用配合的架構再利用可編程延遲線(Programmable Delay line)來配置環形震盪器,在不影響比較策略下所獲得的回應的前提下,讓選擇的環形震盪器對兩者的頻率差異更加明顯,以同時滿足獨特性及可靠性,提高FPGA PUF的性能。方法的結果間漢明距離為49.3%,在溫度0℃到70℃間平均內漢明距離為0.4%。
英文摘要 Physical Unclonable Function is used for device authentication and key generation. It can generate secret information on the chip without storing critical information. The ring oscillator has attracted much attention because it is easy to implement on the Field Programmable Gate Array (FPGA). However, due to structural differences and regional potential deviations, not all challenge and response pairs are suitable for use, and when we choose a highly unique response, the change in the operating environment will lead to instability. The ring oscillator is based on the adjacency-comparison which use cooperative architecture and utilize Programmable delay line to configure the ring oscillator, without affecting the response obtained under the comparison strategy. So that the selected ring oscillator pair frequency difference is more significant at the same time for improving the performance of the FPGA PUF. The method can reach 0.4% intra-HD and 49.3% inter-HD.
論文目次 摘   要 i
ABSTRACT ii
Content iii
List of Tables v
List of Figures vi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis organization 2
Chapter 2 Background 4
2.1 PUF and Ring Oscillator PUF on FPGA 4
2.2 PUF Enrollment and Reconstruction 5
2.3 PUF Quality 7
2.3.1 Uniqueness 7
2.3.2 Reliability 8
2.3.3 Bit-aliasing 8
2.4 Runtime Decision 9
2.5 Ring Oscillator Delay Model 10
2.6 FPGA Fabric 11
2.7 Systematic variation on FPGA 13
2.7.1 Hard Macro 13
2.7.2 Fabric difference 14
2.7.3 Spatial dependence 15
2.7.4 Comparison Strategy 16
2.7.5 Inject locking 17
2.8 Relation between temperature and reliability 18
2.9 Reliability Enhance 19
2.9.1 1-out-of k scheme 19
2.9.2 Configuration with MUX 20
2.9.3 Programmable Delay Line 22
Chapter 3 Adjacence-based Comparison and Configurable RO 25
3.1 Conflict between Uniqueness and Reliability 25
3.2 Adjacency comparison 28
3.3 Mux tree balance 29
3.4 Configuration enhancement 30
Chapter 4 Experimental Results 32
4.1 Systematic variation 32
4.2 Inject locking 35
4.3 PDL behavior 38
4.4 Comparison 42
Chapter 5 Conclusion and Future Work 44
5.1 Conclusion 44
5.2 Future work 44
References 45
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[2] C. Gu, N. Hanley, and M. O’neill, “Improved reliability of FPGA-based PUF identification generator design,” ACM Trans. Reconfigurable Technol. Syst., vol. 10, pp. 20:1–20:23, May 2017.
[3] M. A. Usmani, S. Keshavarz, E. Matthews, L. Shannon, R. Tessier and D. E. Holcomb, "Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 2, pp. 364-375, Feb. 2019
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[5] K. Zhou, H. Liang, Y. Jiang, Z. Huang, C. Jiang, and Y. Lu, “FPGA-Based RO PUF with Low Overhead and High Stability,” Electronics Letters, vol. 55, no. 9, pp. 510–513, 2019.
[6] A. Herkle, H Mandry, J.Becker, and M. Ortmanns, “In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019.
[7] R. Hesselbarth, F. Wilde, C. Gu, and N. Hanley, “Large scale ro puf analysis over slice type, evaluation time and temperature on 28nm xilinx fpgas,” in 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), April 2018, pp. 126–133.
[8] A. Herkle, H Mandry, J.Becker, and M. Ortmanns, “In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019.

[9] A. Maiti and P. Schaumont, "Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive," Springer-Verlag New York, vol. 24, 2011, pp 375-397.
[10] D. Merli, F. Stumpf, and C. Eckert, “Improving the quality of ring oscillator PUFs on FPGAs,” in 5th Workshop on Embedded Systems Security (WESS’2010). Scottsdale, AZ, USA: ACM, October 2010
[11] M. Majzoobi, F. Koushanfar and S. Devadas, "FPGA PUF using programmable delay lines," 2010 IEEE International Workshop on Information Forensics and Security, Seattle, WA, 2010, pp. 1-6.
[12] 7 Series FPGAs Configurable Logic Block - UG474, Xilinx, Sep. 2016
[13] W. Liu, Y. Yu, C. Wang, Y. Cui, and M. O'Neill, "RO PUF Design in FPGAs with New Comparison Strategies", Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 77-80,2015.
[14] K. A. Asha, A. Patyal and H. Chen, "Generation of PUF-Keys on FPGAs by K-means Frequency Clustering," 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, 2018, pp. 44-49.
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