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系統識別號 U0026-0108201717354100
論文名稱(中文) 於矽穿孔結構上製備氧化鎳電阻式記憶體之研究
論文名稱(英文) The prospective study of nickel oxide-based resistive random-access memory (RRAM) fabricated on the thru-silicon via (TSV) structure.
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 105
學期 2
出版年 106
研究生(中文) 鄭佳航
研究生(英文) Chia-Hang Cheng
學號 Q16041034
學位類別 碩士
語文別 中文
論文頁數 96頁
口試委員 指導教授-莊文魁
口試委員-蘇炎坤
口試委員-張守進
口試委員-王水進
口試委員-薛丁仁
中文關鍵字 電阻式記憶體  矽穿孔  三維積體電路  氧化鎳 
英文關鍵字 Resistive Random Access Memory (RRAM)  Through Silicon Via (TSV)  Three-dimensional integrated circuits  nickel oxide 
學科別分類
中文摘要 矽穿孔(Through Silicon Via, TSV)技術利用垂直鑽孔導通的方式連接晶片,相較於打線(wire bonding)技術大幅縮短導線長度,提供更低的電阻與電感效應,降低功率損耗並增進元件的效能,且擁有異質整合等優點,於應用方面能與各式半導體元件整合。而在記憶體發展趨勢中,電阻式記憶體(Resistive Random Access Memory, RRAM)被視為下個世代的非揮發性記憶體,其相較於快閃記憶體(Flash Memory),擁有結構簡單、較小的面積、操作速度快、低寫入功耗、非揮發性與高操作週期等優點,同時也與CMOS製程相容,在產業界與學術領域中越來越多人投入RRAM的研究中。綜合上述所提及,我們可以預測TSV技術與RRAM元件終將進行整合,故本論文之目的在於將TSV技術與RRAM元件整合並進行探討。
將RRAM整合於TSV之前,首先我們製作四種不同電極結構之氧化鎳RRAM,其中氧化鎳薄膜是利用射頻磁控濺鍍法(Radio Frequency Magnetron Sputtering Method)成長,量測此四種結構RRAM之電流電壓掃描曲線,並探討其穩定性。最後選擇上下電極皆為白金結構的RRAM整合於TSV,並成功量測其電流電壓特性曲線,在耐用度測試上穩定達到100次循環,高低阻態在0.1V時的電流比值達到兩個階數(order),其寫入電壓(set voltage)與拭去電壓(reset voltage)呈現穩定常態分佈,接著在記憶時間(retention time)可靠度方面的量測,其記憶窗口(memory window)在經過10000秒的量測後,依舊保持其優異儲存特性,最後利用曲線擬合(curve fitting)的方式進行內部漏電流機制的探討。
英文摘要 Through Silicon Via (TSV) technology vertically connects the chips arranged in stack, which helps to enhance the chip performance by greatly shortening the length of the conducting wire. On the other side, as the development of memory constantly aiming for faster memory devices with high storage capacity, Resistive Random Access Memory (RRAM) is considered the nonvolatile memory of next generation. It is foreseeable in a near future that the possibility of integrating the TSV platform with RRAM components may one day come to a reality! Therefore, the purpose of this thesis is to evaluate the plausibility of this merger. First, nickel oxide based RRAMs with four different electrode structures were fabricated, of which nickel oxide was grown using a radio frequency magnetron sputtering method. The properties and stability of these four different types of RRAM were evaluated. The platinum was chosen as the top and bottom electrode for RRAM integrated with the TSV structure, and the resultant current-voltage characteristics were duly measured. As for the endurance test, it was stably enough to achieve 100 cycles, and the current contrast ratio between the high and low resistance setting at 0.1V was found to be at least two orders of magnitude. Its set and reset voltage showed a stable normal distribution. Furthermore, the retention time reliability test also demonstrated that the memory window still maintains its excellent storage characteristics after more than 10,000 seconds. Finally, a series of curve fittings was applied to analyze the XPS data set in order to discuss the internal leakage current mechanism.
論文目次 目錄
中文摘要 I
英文摘要 III
誌謝 XI
目錄 XIII
表目錄 XVIII
圖目錄 XIX
第一章 緒論 1
1.1背景與動機 1
1.2 TSV發展歷史簡述 4
1.2.1 TSV市場應用分析 6
1.3 電阻式記憶體歷史簡述 9
參考文獻 15
第二章 文獻回顧 20
2-1三維矽穿孔製程 20
2-1-1 導孔的蝕刻(Via Etching) 21
2-1-1-1雷射鑽孔 22
2-1-1-2 Bosch 深反應性離子蝕刻 23
2-1-1-3低温型深反應性離子蝕刻 24
2-1-2 導孔的填充 25
2-2氧化鎳簡介 27
2-3前瞻記憶體簡介 29
2-3-1鐵電記憶體 30
2-3-2磁阻式記憶體 31
2-3-3相變化記憶體 32
2-3-4電阻式記憶體 33
2-4電阻切換的機制 34
2-4-1燈絲理論 34
2-4-2焦耳熱效應 36
2-4-3楊離子效應與陰離子效應 37
2-5絕緣體漏電流傳導機制 39
2-5-1  歐姆傳導(Ohmic Conduction) 39
2-5-2  蕭基發射(Schottky Emission)[43] 40
2-5-3  普爾-法蘭克發射(Poole-Frenkel Emission)[44, 45] 40
2-5-4  空間電荷限制電流(Space Charge Limit Current)[46, 47] 41
2-5-5  穿隧(Tunneling)[48, 49] 42
2-5-6  跳躍傳導(Hopping Conduction)[50] 43
參考文獻 45
第三章 實驗方法與實驗儀器簡介 50
3.1實驗流程 50
3-2 TSV製備實驗步驟 51
3-2-1晶圓清洗 51
3-2-2深蝕刻阻擋層 51
3-2-3曝光顯影 51
3-2-4鋁蝕刻 52
3-2-5低溫型深反應性離子蝕刻 (Cryogenic DRIE) 52
3-2-6成長絕緣層 52
3-2-7擴散阻礙層 52
3-2-8銅晶種層 53
3-2-9曝光顯影定義電鍍範圍 53
3-2-10銅電鍍 53
3-2-11化學機械研磨(Chemical Mechanical Planarization, CMP) 54
3-2-12曝光顯影製作隔離區域 54
3-2-13蝕刻銅與鈦 54
3-3 RRAM製備實驗步驟 55
3-3-1曝光顯影定義RRAM位置 55
3-3-2下電極製作 55
3-3-3成長氧化鎳薄膜 55
3-3-4掀離(lift-off) 56
3-3-5曝光顯影定義上電極位置 56
3-3-6上電極製作 56
3-3-7掀離 56
3-3-8量測作業 56
3-4實驗與量測儀器簡介 57
3-4-1濕式蝕刻清洗系統(Wet bench) 57
3-4-2光罩對準曝光系統(Mask aligner) 58
3-4-3自動塗佈機 59
3-4-4電漿輔助式化學氣相沈積&感應耦合式電漿蝕刻系統(PECVD & ICP) 60
3-4-5水平爐管LPCVD 61
3-4-6熱蒸鍍機(Thermal Evaporation) 62
3-4-7射頻磁控濺鍍機(RF magnetron Sputter) 63
3-4-8電子束蒸鍍機(Electron Beam Evaporation) 64
3-4-9 B1500半導體元件參數分析儀 64
3-4-10掃描式電子顯微鏡(Scanning Electrons Microscope, SEM ) 64
3-4-11化學分析電子光譜儀(X-ray Photoelectron Spectroscopy , XPS) 65
第四章 結果與討論 66
4-1 TSV深蝕刻與銅電鍍之探討 66
4-1-1導孔之深蝕刻 66
4-1-2導孔之銅電鍍 68
4-2氧化鎳薄膜SEM分析與RRAM結構探討 70
4-2-1氧化鎳薄膜SEM分析 70
4-2-2比較不同電極之RRAM結構 72
4-2-2-1 Au/Ni/NiO/Ti結構RRAM 72
4-2-2-2 Al/NiO/Ti結構RRAM 74
4-2-2-3 Ti/NiO/Pt結構RRAM 76
4-2-2-4 Pt/NiO/Pt結構RRAM 79
4-3 TSV架構下之RRAM量測與分析 83
4-3-1 電性量測 83
4-3-2電流傳導機制之曲線擬合分析 90
4-3-3 XPS分析 92
4-3-4 TSV架構之RRAM結果討論 93
參考文獻 94
第五章:結論與未來工作 95
5-1結論 95
5-2未來工作 96
表目錄
表4-1 深蝕刻製程參數 67
表4-2 各沈積層之參數 68
表4-3 NiO薄膜成長之參數表 70
表4-4 各樣品之電極結構表 72
表4-5 四種結構之RRAM電特性比較表 82
圖目錄
圖1-1 2D IC與3D IC封裝比較[6] 2
圖1-2 William Shockleyn提出的三維堆疊晶片示意圖[15] 5
圖1-3 Merlin Smith與Emanuel Stern所提出的TSV結構概念示意圖[16] 5
圖1-4 TSV市場應用預測(資料來源: Yole) 6
圖1-5 以TSV技術封裝CIS [17] 7
圖1-6 NAND Flash垂直堆疊[19] 8
圖1-7電阻式記憶體結構 13
圖2-1 鑽孔製程簡介 (a)先鑽孔製程 (b)中段鑽孔製程 (c)後鑽孔製程 (d) 後端製程後鑽孔[2] 21
圖2-2 Bosch process 流程圖(a)沈積C4F8鈍化層(b)利用離子轟擊垂直去除鈍化層(c)以SF6氣體進行非等向性蝕刻(d)沈積C4F8鈍化層(e)移除鈍化且非等向性蝕刻(f)重複循環(a)-(e)步驟[7] 23
圖2-3 Cryogenic DRIE 之物理與化學運作機制圖[10] 24
圖2-4 (a)傳統電鍍法, (b)由底部往上電鍍法[18] 26
圖2-5 氧化鎳晶格結構示意圖[20] 27
圖2-6 不同通氧量之氧化鎳薄膜XRD量測圖(a)5%, (b)10%, (c)16.7%與(d)20%通氧量[27] 28
圖2-7 電滯特性曲線圖[30] 30
圖2-8 MRAM讀取機制示意圖[31] 31
圖2-9相變化記憶體之(a)結構與(b)操作原理[33] 32
圖2-10 以金屬氧化層為例之RRAM結構示意圖[34] 33
圖2-11導電細絲的形成與斷裂示意圖[37] 35
圖2-12雙極性導電細絲模型RRAM之I-V曲線圖。插圖(A)-(C)表示三種不同阻態的模型。[38] 36
圖2-13焦耳熱效應之示意圖[39] 37
圖3-1 TSV製作流程 50
圖3-2 RRAM製作流程(以Pt電極為例) 51
圖3-3濕式蝕刻清洗系統(Wet bench) 58
圖3-4光罩對準曝光系統(Mask Aligner)。 59
圖3-5自動化光阻塗佈(Track) 60
圖3-6電漿輔助式化學氣相沈積&感應耦合式電漿蝕刻系統(PECVD & ICP) 61
圖3-7 高溫及低壓爐管(horizontal furnace) 62
圖3-8熱蒸鍍機 (Thermal Evaporation) 63
圖4-1 直徑200μm導孔深蝕刻後截面圖 67
圖4-2 導孔電鍍後之截面圖 69
圖4-3增加光澤劑劑量電鍍後之截面圖 69
圖4-4電鍍電流為0.1 A電鍍後截面圖 69
圖4-5 NiO膜表面SEM圖 71
圖4-6 NiO膜截面SEM圖 71
圖4-7 Au/Ni/NiO/Ti RRAM之電流電壓(I-V)特性圖 73
圖4-8 Al/NiO/Ti結構RRAM之I-V曲線(前五十次) 75
圖4-9 Al/NiO/Ti結構RRAM之I-V曲線(後五十次) 75
圖4-10 Al/NiO/Ti結構RRAM之開關比 76
圖4-11 Ti/NiO/Pt結構RRAM之I-V曲線(前五十次) 77
圖4-12 Ti/NiO/Pt結構RRAM之I-V曲線(後五十次) 78
圖4-13 Ti/NiO/Pt結構RRAM之開關比 78
圖4-14 Pt/NiO/Pt結構RRAM之I-V曲線(前五十次) 80
圖4-15 Pt/NiO/Pt結構RRAM之I-V曲線(後五十次) 80
圖4-16 Pt/NiO/Pt結構RRAM之開關比 81
圖4-17 量測手法示意圖 (a)單獨量測RRAM元件 (b)下電極經TSV導電至背面之量測 84
圖4-18 單獨量測RRAM之I-V曲線 85
圖4-19 單獨量測RRAM之開關比 85
圖4-20 RRAM整合TSV之I-V曲線 86
圖4-21 RRAM整合TSV之耐用度測試 87
圖4-22 100次Cycles高低阻態電流之累積機率圖 88
圖4-23 Set voltage和reset voltage 分佈圖 89
圖4-24 記憶時間(retention time)量測 89
圖4-25 RRAM整合TSV之電流機制擬合 91
圖4-26擬合結果(a)HRS歐姆傳導機制擬合(b)LRS歐姆傳導機制擬合(c) F-N tunneling傳導機制擬合(d) Hopping conduction機制擬合 92
圖4-27 XPS頻譜分析(a) Ni2p3/2之XPS頻譜分析(b)薄膜內部之鎳原子與氧原子比例 93
圖5-1 RRAM陣列與TSV整合示意圖 96
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