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系統識別號 U0026-0102201914585200
論文名稱(中文) 無需頻率合成器之 2.4 GHz 低中頻接收機前端電路
論文名稱(英文) A Synthesizer-Free 2.4 GHz Low-IF Receiver Front-End
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 107
學期 1
出版年 108
研究生(中文) 周承潣
研究生(英文) Cheng-Min Chou
電子信箱 frank3497770@gmail.com
學號 Q36044573
學位類別 碩士
語文別 英文
論文頁數 135頁
口試委員 指導教授-鄭光偉
口試委員-黃尊禧
口試委員-莊惠如
口試委員-洪子聖
中文關鍵字 接收機  前端電路  低功耗  自混頻  頻率合成器 
英文關鍵字 Receriver  Front-End  Low power  Self-Mixing  Frequency Synthesizer 
學科別分類
中文摘要 本論文提出一個創新的接收機架構,透過自混頻的方式省去高頻的振盪器以及頻率合成器(Frequency Synthesizer)所需額外的功率消耗,操作頻率為24億赫茲,供應電壓為1.2伏特,轉換增益達到40.16 dB,雜訊指數為7.16 dB,整體的功率消耗為2毫瓦。 在射頻前端電路裡,透過將接收到的射頻訊號(RF)與外部產生的中頻頻率(IF)的訊號進行混頻,將資料載到產生的射頻加減中頻(RF±IF)的訊號上;再透過第二次混頻將射頻加減中頻的訊號與接收到的射頻訊號進行混頻,將資料載回到中頻上完成前端電路的工作。
由於傳統的超外差接收機(Super Heterodyne Receiver)以及同差式接收機(Homodyne Receiver)為了將不同通道上的訊號降頻到一樣的中頻或是基頻上,會需要頻率合成器精準地控制本地振盪器的頻率,而代價就是額外的功率消耗以及面積;因此本論文希望透過上述的自混頻技巧來實現一個不需要頻率合成器即能控制降頻後中頻位置的接收機架構。本接收機電路除了偏壓電路的電阻外其餘皆完全製作於積體電路且使用台積電90奈米製程,晶片面積為1.34×1.4毫米平方。
英文摘要 This thesis presents an innovative receiver architecture, called self-mixing technique, that eliminates the power consumption of high-frequency oscillators and frequency synthesizers. The operating frequency is 2.4 GHz and the receiver front-end achieves 40.16 dB Conversion Gain, 7.1 dB Noise Figure while consuming 2 mW from a 1.2 V supply voltage.
By mixing the received RF signal with an externally generated intermediate frequency (IF) signal. The RF signal is converted to RF plus/minus intermediate frequency (RF±IF). Next, through the second mixing, mixed with the received RF signal, RF±IF is down-convert to the intermediate frequency, as the baseband.
In order to cover the N-channel bands, traditional Super-Heterodyne Receiver and Homodyne Receiver needs frequency synthesizers to precisely control the local oscillator (LO) to down-convert the data to the same IF band, and the burden is the power consumption and chip size. This work is focused on realizing a receiver architecture without a frequency synthesizer for saving the power consumption. A prototype is fabricated in 90 nm TSMC technology. The chip area is 1.34 × 1.4 mm2.
論文目次 Table of Contents
Chapter 1 Motivation 1
1.1 Thesis Organization 6
Chapter 2 Introduction 7
2.1 Specs of Receiver front-ends 7
2.1.1 Impedance Matching 7
2.1.2 Conversion Gain 9
2.1.3 Noise Figure 9
2.1.4 Effects of non-linearity 11
2.2 Bluetooth Low Energy Standard 14
Chapter 3 Literature Review 16
3.1 Conventional Receiver Front-End 16
3.1.1 Super-Heterodyne Receiver 16
3.1.2 Direct Conversion Receiver 17
3.1.3 Low-IF architecture 19
3.2 Low Power RX without Frequency Synthesizer 21
3.2.1 Super Regenerative receiver 21
3.2.2 Carrier-Reinforcement systems 25
3.3 Circuit level of low power implementation 26
3.3.1 Current-Reused Techniques 26
3.3.2 Low VDD Architecture 29
Chapter 4 Proposed Receiver Front-End 32
4.1 Realization Concept 32
4.1.1 Problems and Solutions 34
4.2 System Consideration 41
4.2.1 Main Signal Path 41
4.2.2 Second Path 44
4.3 Circuit Implementation 45
4.3.1 Low Noise Amplifier (LNA) (Single-Ended Version) 45
4.3.2 Low Noise Amplifier (LNA) (Differential Version) 52
4.3.3 Complementary Current Reused Mixer with Current Bleeding Technique 79
4.3.4 RF±IF Generator 84
4.3.5 Output Buffer 91
Chapter 5 Simulation Results 93
5.1 Post-Layout Simulation Results of Proposed RX Front-End 94
5.1.1 Low Noise Amplifier (LNA) (Differential Version) 95
5.1.2 RF Amplifier 99
5.1.3 RF±IF Amplifier 101
5.1.4 Complementary Current-Reused Mixer 102
5.1.5 Entire System 103
Chapter 6 Measurement Results 107
6.1 Low Noise Amplifier (Single-Ended Version) 107
6.1.1 Measurement Results 108
6.2 RX Front-End Measurement 111
6.2.1 LNA Measurement Setup 114
6.2.2 Entire System Measurement Setup 116
6.2.3 Measurement Results 119
Chapter 7 Conclusion and Future Works 124
7.1 Conclusion 124
7.2 Future Works 125
7.2.1 Proposed S2D LNA 125
7.2.2 Proposed Synthesizer-Free RX Front-End 128
Reference 130

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