進階搜尋

 
查詢範圍:「   」
顯示範圍:第筆 論文書目資料
顯示格式:全部欄位
共 9 筆
------------------------------------------------------------------------ 第 1 筆 ---------------------------------------------------------------------
系統識別號 U0026-0407201013395900
論文名稱(中文) 互補式金氧半導體奈米製程故障分析之研究
論文名稱(英文) The Study of Complementary Metal Oxide Semiconductor Failure Analysis in Nano Process
校院名稱 成功大學
系所名稱(中) 電機工程學系專班
系所名稱(英) Department of Electrical Engineering (on the job class)
學年度 98
學期 2
出版年 99
研究生(中文) 賴世偉
學號 n2795108
學位類別 碩士
語文別 英文
口試日期 2010-06-24
論文頁數 92頁
口試委員 指導教授-張守進
口試委員-陳志方
口試委員-方炎坤
口試委員-陳世志
口試委員-陳進祥
關鍵字(中) 故障分析
故障點定位
樣品處理
樣品檢測
關鍵字(英) Failure Analysis
Failure Site Localization
Sample Preparation
Sample Inspection
學科別分類
中文摘要 由於國內故障分析技術之研究並不多,所以本論文主要是建立一個完整的故障分析流程,深入探討互補式金氧半導體在奈米製程故障分析上所遇到的挑戰。首先探討各個故障點的定位技術、優缺點以及舉實例來加以說明。故障點分析的技術有液晶熱反應偵測術 (liquid crystal microscopy) 、微光偵測術 (photon emission microscopy) 、熱光束產生電阻變化偵測術 (optical beam induced resistance change) 和靜態隨機儲存記憶體利用測試模組的故障點分析 (static random access memory of bitmap programming) ,由於奈米製程積體電路的物理上的限制,使的故障點的定位變的非常的困難,針對奈米製程故障點定位,另外探討一個新的技術,互補式金氧半導體積體邏輯電路利用測試模組的故障點分析 (diagnosis) ,最後針對各故障點定位技術做一個比較。
接下來簡單探討幾種故障分析樣品處理的方法,有研磨法、聚焦離子束電路修改法 (focused Ion beam circuit repair) 、濕蝕刻、乾蝕刻等,研究其在奈米製程上故障分析遇到的挑戰。另外探討物性上樣品檢視的幾種工具如光學顯微鏡 (optical microscope) 、掃描式電子顯微鏡 (scanning electron microscope) 、聚焦離子束切割 (focused Ion beam X-section) 、穿透式電子顯微鏡 (transmission electron microscope) 、掃描穿透式電子顯微鏡 (scanning transmission electron microscope) 、能量散佈X光譜儀 (Energy Dispersive Spectroscopy) ,接下來是電性上樣品檢視的幾種工具如掃描式電容量測 (scanning capacitor microscopy) 、被動式電壓對比 (passive voltage contrast) 等。最後是因應奈米製程在電性上樣品檢測的兩個新的技術與應用,一個是傳導式原子力量測 (conductive atom force microscopy) ,研究如何偵測出金氧半導體氧化層的缺陷,研究如何偵測出連接導線高阻值的問題,最後是奈米探針量測 (nano-probing) 的技術,兩個實例應用研究如何偵測出金氧半導體源極到汲極線缺陷的問題,並討論其機制。
英文摘要 The study of failure analysis (FA) is rare internal. Thus the purpose of this thesis is to setup a complete FA flow and to study the challenges of couple metal oxide semiconductor (CMOS) FA in nano process. First to study each technique of failure site localization, advantages, disadvantages and limitations and illustrated by real cases. The techniques of failure site localization are liquid crystal microscopy, photon emission microscopy, optical beam induced resistance change and static random access memory of bitmap programming. Because of the physical limitation of nano process integrated circuit (IC), failure site localization becomes more and more difficult. To study a new technique which is FA of CMOS logic IC by testing pattern, called diagnosis.
Next, simply introduces several methods of FA of sample preparation as top lapping, focused Ion beam (FIB) circuit repair, wet etching and dry etching and discusses the challenges of FA in nano process. Then simply introduces several methods of sample inspection analysis in physically as optical microscope, scanning electron microscope, FIB X-section, transmission electron microscope, scanning transmission electron microscope and energy dispersive spectroscopy and in electrically as scanning capacitor microscopy and passive voltage contrast. Finally, two new techniques and applications of sample inspection analysis in electrically in order to analysis more accurate in nano process, one is conductive atom force microscopy, to study CMOS gate oxide defect localization and inter connection high resistance detection. Another is nano-probing technique, to study two real cases of applications of source to drain dislocation detection and discusses their mechanisms.
論文目次 Content
Abstract (in Chinese) I
Abstract (in English) III
Acknowledgement V
Contents VI
Table Captions IX
Figure Captions X

CHAPTER 1 Introduction 1
1-1. Process Proceeding 1
1-2. Failure Analysis Flow 2
CHAPTER 2 Failure Site Localization 7
2-1. Liquid Crystal Microscopy 7
2-1-1. Theory and System Setup 7
2-1-2. Case Study 8
2-1-3. Advantage and Disadvantage 8
2-2. Photon Emission Microscopy 9
2-2-1. Theory and System Setup 9
2-2-2. Case Study 10
2-2-3. Advantage and Disadvantage 10
2-3. Optical Beam Induce Resistance Change 11
2-3-1. Theory and System Setup 11
2-3-2. Case Study 13
2-3-3. Advantage and Disadvantage 13
2-4. Bitmap 14
2-4-1. Theory and System Setup 14
2-4-2. Case Study 14
2-4-3. Advantage and Disadvantage 15
2-5. Diagnosis 16
2-5-1. Theory and System Setup 16
2-5-2. Case Study 16
2-5-3. Advantage and Disadvantage 17
2-6. Comparison 17
CHAPTER 3 Challenges of Sample Preparation and Inspection Analysis 36
3-1. Sample Preparation 36
3-1-1. Lapping 36
3-1-2. Focused Ion Beam Circuit Repair 37
3-1-3. Wet Etching 37
3-1-4. Dry Etching 38
3-2. Physical Inspection Analysis 39
3-2-1. Optical Microscope 39
3-2-2. Scanning Electron Microscope 40
3-2-3. Focused Ion Beam X-section 41
3-2-4. Transmission Electron Microscope 41
3-2-5. STEM/EDS 42
3-3. Electrical Inspection Analysis 43
3-3-1. Scanning Capacitor Microscopy 43
3-3-2. Passive Voltage Contrast 44
CHAPTER 4 Applications of New Electrical Inspection Analysis 57
4-1. Conductive Atom Force Microscopy 57
4-1-1. System 58
4-1-2. Application I: Gate Oxide Defect Localization 58
4-1-3. Application II: Inter Connection High Resistance Detection 59
4-1-4. Advantage and Disadvantage 60
4-2. Nano-probing 61
4-2-1. System 62
4-2-2. Application I: Specific Source to Drain Dislocation Detection 63
4-2-3. Application II: Specific Source to Drain Dislocation Detection 64
4-2-4. Advantage and Disadvantage 65
4-3. Comparison 66
CHAPTER 5 Conclusion and Future Work 83
5-1. Conclusion 83
5-2. Future Work 83
Reference 86
參考文獻 [1] Texas Instruments, “The Chip that Jack Built”, (HTML), accessed May 29, (2008).
[2] Moore, Gordon E., "Cramming more components onto integrated circuits", (1965).
[3] Wgsimon, “CPU Transistor Counts and Moore’s Law”, (HTML), accessed December 29, (2008).
[4] Morris Chang, “IC ‘megatrends’ point to post-Moore’s Law era”, speech at the Taiwan+China Semiconductor Outlook Conference in San Joe, Sept. 15, (2003).
[5] Taiwan Semiconductor Manufacturing Company, “2008 Business Overview”, pp. 8, (2008).
[6] De Gennes, P.G. and Prost, J, “The Physics of Liquid Crystals”, Oxford: Clarendon Press., (1993).
[7] Chandrasekhar, S., “Liquid Crystals”, Cambridge: Cambridge University Press., (1992).
[8] H.C. Huang, “The Comparison of Failure Analysis Technologies in Complementary Metal Oxide Semiconductor Integrated Circuit”, Adv. Master., pp. 10, (2006).
[9] A. Csendes, V. Székely, M. Kerecsen-Rencz, “Thermal mapping with liquid crystal method, Microelectronic Engineering”, V.31, pp.281-290 (1996).
[10] Christian Boit, “Fundamentals of photon emission(PEM) in silicon – electroluminesence for analysis of electronic circuit and device functionality”, Microelectronics Failure Analysis Desk Reference 5th Edition, pp. 357-369.
[11] S. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, New York, (1981).
[12] Donald A. Neamen, “Semiconductor Physics & Devices”, McGraw Hill, Third Edition, Dec., (2002).
[13] B. Marchand, D. Blachier, C. Leroux, G. Ghibaydo, F. Balestra, G. Reimbold, “Generation of Hot Carries by Secondary Impact Ionization in Deep Submicron Devices: Model and Light Emission Characteristics”, IEEE 38th Annual International Reliability Physics Symposium, San Jose, California, pp. 93-97, (2000).
[14] Bram Kruseman, Martijn Goossens, Victor Zieren, “Photon Emission Microscopy in 90nm CMOS Technologies”, 30th ISTFA, pp. 210-215, Nov., (2004).
[15] Daniel L. Barton, Edward I. Cole Jr., Karoline Berhard-Hofer, “Flip-Chip and Backside Sample Preparation Techniques“, Microelectronics Failure Analysis, pp. 43 –49, Oct., (2004).
[16] J. Colvin, “BGA and advanced package Wire to Wire bonding for Backside emission microscopy”, International Symposium Testing and Failure Analysis proceedings, pp.365-375, (1999).
[17] C.H. Wang, S.W. Lai, Z.H. Lee, J.H. Chou, “The Enhancement of Abnormal Photon Emission Identification for Advanced Processes using a Backside Cooling PEM System”, 31th ISTFA, pp. 241-244, (2005).
[18] Hamamatsu Inc., ”Phemos Series General Catalogue”, (HTML), pp. 6, (2009).
[19] Nikawa, K; Tozaki, S, "Principles Novel OBIC Observation Method for Detecting Defects in Al Stripes Under Current Stressing", Proceedings of the 19th International Symposium for Testing and Failure Analysis (Materials Park, Ohio: ASM International), pp. 303–310, (1993).
[20] Cole, E. I; Tangyunyong, P; Barton, D.L, "Backside Localization of Open and Shorted IC Interconnections", 36th Annual International Reliability Physics Symposium (The Electron Device Society and the Reliability Society of the Institute of Electrical and Electronics Engineers, Inc.), pp. 129–136, (1998).
[21] Thomas Johann Seebeck (1770-1831), ERIC Weisstein’s World of Biography, Wolfram Research, http://scienceworld.wolfram.com
[22] Falk, R.A, "Advanced LIVA/TIVA Techniques", Proceedings of the 27th International Symposium for Testing and Failure Analysis (Materials Park, Ohio: ASM International), pp. 59–65, (2001).
[23] Michael R. Bruce, Victoria J. Bruce, David H. Eppes, Jacob Wilcox, “Soft defect localization (SDL)”, ISTFA, p21-27, (2002).
[24] B F Hann, “An approach to Electrical Conductivity in Solids”, Physics Education, IOP Electronic Journals, pp.207-211, (1969).
[25] Hamamatsu Inc., ”uAMOS-200 Catalogue”, (HTML), pp. 2, (2009).
[26] K. Nikawa, S. Inoue, “Various Contrasts Identifiable from the Backside of a Chip by 1.3um Laser”, ISTFA, pp. 387-392, (1996).
[27] S. J. Bennett, “The thermal expansion of copper between 300 and 700K”, Journal Physics D: Applied Physics 11 pp. 777-780, (1978).
[28] David Hodges, Horace Jackson, Resve Saleh, “Analysis and Design of Digital Integrated Circuits”, McGraw Hill published, 3rd edition, pp. 359-361, July, (2003).
[29] Kinoshata, K., Saluja, “Built-in Testing of Memory using on-chip compact testing scheme”, Proc. Of IEEE International Test Conference, (1984).
[30] C. Brillert, C. Burmer, P. Egger, “SRAM Failure Analysis Flow”. 27th ISTFA, (2001).
[31] P. Egger, C. Burmer, “SRAM Failure Analysis Strategy”, 29th ISTFA, Nov., (2003).
[32] J.-Y. Glacet, F. Lee, “Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement”, 26th ISTFA, (2000).
[33] Montgomery Phister, “Logical Design of Digital Computers”, Wiley., pp. 128, (1958).
[34] J.B. Khare, W. Maly, S. Griep, D. Schmitt-Landsiedel, “Yield-oriented computer-aided defect diagnosis”, IEEE Trans. On Semi. Manufacturing, Vol. 8, Issue 2, pp. 195-206, May, (1995).
[35] C. Hora, R Segersm S. Eichenberger, M, Lousberg, “An Effective Diagnosis Method to Support Yield Improvement”, Proc. Intl. Test Conf., (2002).
[36] W. May, A. Gattiker, T. Zanon, T. Vogels, R.D. Blanton, T. Storey, “Deformation of IC Structure in Test and Yield learning”, Proc. Intl. Test Conf., pp. 856-865, (2003).
[37] D. Appello, A. Fudoli, V. Tancorre, “Understanding Yield Losses in Logic Circuits”, IEEE Design and Test of Computers, Vol.21, No.3, pp. 208-215, May-June, (2004).
[38] A. Leininger, P. Muhmenthaler, W.T. Cheng, N. Tamarapalli, W. Yang, H. Tsai, “Compression Mode Diagnosis Enables High Volume Monitoring Diagnosis Flow”, ITC, Paper 7.3, (2005).
[39] Jayanth Mekkoth, Murali Krishna, Jun Qian, “Yield Learning with Layout-aware Advanced Scan Diagnosis”, 32th ISTFA, (2006).
[40] J. Waicukauski, E. Lindbloom, “Failure Diagnosis of Structured Circuits”, IEEE Design and Test of Computer, Vol. 6, No.4, pp. 49-60, (1989).
[41] H. Balachandran, J. Parker, D. Shupp, K. Butler, C. Force, J. Smith, “Correlation of logical failures to a suspect process step”, Proc. Intl. Test Conf., pp. 458-466, (1999).
[42] A. Kinra, H. Balachandran, R. Thomas, J. Carulli, “Logic mapping on a microprocessor”, Proc. Intl. Test Conf., pp. 701-710, (2000).
[43] R. D. Blanton, “Failure Diagnosis using Fault Tuples”, Proc. Of IEEE Latin American Test Workshop, pp. 253-257, (2001).
[44] T. Bartenstein, D. Heaberlin, L. Huisman, D. Sliwinki, “Diagnosis Combinational Login Designs using the Single Location At-A-Time (SLAT) Paradigm”, Proc. Intl. Test Conf., pp. 287-296, (2001).
[45] W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, J. Rajski, “Computer independent direct diagnosis”, Proc. Of Asian Test Symp., pp. 15-17, (2004).
[46] D. Bodoh, A. Blakely, T. Garyet, “Diagnostic Fault Simulation for the Failure Analysis”, Proc. Intl. Symp. For Test and Failure Analysis, (2004).
[47] R. Desineni, R.D. Blaton, “Diagnosis of Arbitrary Defects using Neighborhood Function Extraction”, Proc. Of VLSI Test Symp., (2005).
[48] C. Eddleman, N. Tamarapalli, W.-T. Cheng, “Advanced Scan Diagnosis based Fault Isolation and Defect Identification for Yield Learning”, Proc. Of ISTFA, (2005).
[49] C. Smith, K Symond, “Novel Deprocessing Techniques to Analyze Gate Level Defects”, ISTFA, pp. 275-278, (1995).
[50] Katarina Logg., “Optical Microscopy”, Chalmers Dept. Applied Physics, pp. 4, (2006).
[51] Hitachi High Technologies America, Inc., “S-5500 In-Lens FE SEM”, (HTML), accessed (2009).
[52] V. Castaldo, C.W. Hagen, B. Rieger and P. Kruit, “Sputtering limits versus signal-to-noise limits in the observation of Sn balls in a Ga+ microscope” J. Vac. Sci. Tech. B26, p. 2107, (2008).
[53] J. Orloff, L.W. Swanson and M. Utlaut, “Fundamental Limits on Imaging Resolution in Focused ion Beam Systems”, J. Vac. Sci. Tech. B14, p. 3759, (1996).
[54] Carter, C. B., ”Transmission Electron Microscopy”, 1 - Basics. Plenum Press., (1996).
[55] Jon C. Lee, B.H. Lee, “The Versatile Application for In-situ Lift-out TEM Sample Preparation by Micromanipulator and Nanomotor”, ISTFA, (2005).
[56] Crewe, Albert V, Isaacson, M. & Johnson, D., "A Simple Scanning Electron Microscope", Rev. Sci. Inst. 40: 241–246., (1969).
[57] Digital Instrument Veeco Metrology, “Scanning Capacitor Microscopy (SCM)”, Support Note No. 289, Rev. A, pp. 289-7, (2000).
[58] Natasja Duhayon, “Experiment study and optimization of scanning capacitance microscopy for two-dimensional carrier profiling of submicron semiconductor device”, thesis of PhD, June, (2006).
[59] James R.Beall, “Voltage Contrast Techniques and Procedures”, Microelectronic Failure Analysis Desk Reference 3rd Edition, pp. 153-161. (1997).
[60] David P. Vallett., "IC Failure Analysis: The Importance of Test and Diagnostics", IEEE Design and Test of Computers, vol. 14, no. 3, pp. 76-82, July-September, (1997).
[61] H. Seiler, “Secondary Electron Emission in the Scanning Electron Microscope”, Journal of Applied Physics, 54, pp. R1-R8, (1983).
[62] Newbury, D.E., Joy, D.C., Echlin, P., Fiori, C.E., and Goldstein, J.I., “Advanced Scanning Electron Microscopy and X-Ray Microanalysis”, Plenum, New York, (1986).
[63] H.C. Huang, “The Comparison of Failure Analysis Technologies in Complementary Metal Oxide Semiconductor Integrated Circuit”, Adv. Master., pp. 70, (2006).
[64] R. Rosenkranz, “FIB assisted localization and preparation of gate oxide fails”, EFUG, (2002).
[65] A.N. Campbell, J.M. Soden, “Voltage Contrast in the FIB as a Failure Analysis Tool”, Microelectronic Failure Analysis Desk Reference 4th Edition, pp. 161-167, (1999).
[66] G. Binnig, H. Rohrer, “Scanning tunneling microscopy”, IBM Journal of Research and Development, (1986).
[67] Jon C. Lee and J. H. Chuang, “Fault localization in contact level by using conductive atomic force microscopy”, 29th International Symposium for Testing and Failure Analysis, (2003).
[68] C. Smith, K Symond, “Novel Deprocessing Techniques to Analyze Gate Level Defects”, ISTFA, pp. 275-278, (1995).
[69] Cheng-Piao Lin, Cheng-Hsu Wu and Cheng-Chun Ting, “A novel electrical test by C-AFM to differentiate gate-to-SD gate oxide short from non-gate oxide short defect in real products”, 30th ISTFA, (2004).
[70] Z.H. Lee, C.J. Lin, S.W. Lai and J.H. Chou, “Gate Oxide Defect Localization and Analysis by Using Conductive Atomic Force Microscopy”, 31th ISTFA, pp. 235-238, (2005).
[71] Thong, J., "Electron Beam Probing". Microelectronics Failure Analysis. ASM International. pp. 438–443, (2004).
[72] Kolachina, S., "Introduction to Laser Voltage Probing (LVP) of Integrated Circuits". Microelectronics Failure Analysis. ASM International. pp. 426–430, (2004).
[73] Desplats, R.; Eral, A.; Beaudoin, F.; Perdu, P.; Chion, A.; Shah, K.; Lundquist, T., "IC Diagnostic with Time Resolved Photon Emission and CAD Auto-channeling". Proceedings from the 29th International Symposium for Testing and Failure Analysis. Materials Park, Ohio: ASM International. pp. 45–54, (2003).
[74] R. Rosenkranz, S. Döring, W. Werner, L. Bartholomäus and S. Eckl, “Active Voltage Contrast for Failure Localization in Test Structures”, ASM International, (2006).
[75] Multiprobe, Inc., “PicoCurrent imaging using the Multiscan Atomic Force Probe”, (HTML), (2007).
[76] Frank siegelin, Anton Stuffer, “Dislocation related leakage in advanced CMOS devices”, 31th ISTFA, pp. 59-63, Nov., (2005).
[77] C.H. Wang, C.M. Shen, C.J. Lin, Z.H. Lee, J.H. Chou, “the study and methodology of defects isolation for contacts of non-isolated active regions on new logic designs”, 31th ISTFA, pp. 479-483, Nov., (2005).
[78] S.C. Liou, J.H. Chuang, J.C. Lee, “The physical failure analysis of Iddq and Iddq fail in 90nm logic products”, 12th IPFA, pp. 47-51, (2005).
[79] C.H. Wang, S.W. Lai, C.Y. Wu, B.T. Chen, J.Y. Chiou, J.H. Chou, “The failure analysis of specific source-to-drain dislocation and case study”, 34th ISTFA, pp. 245-248, Nov., (2008).
[80] Nathan Wang, Susan Li, “Application of 3-D Transmission Electron Microscopy in Semiconductor Device Analysis”, EDFA, (2008).
[81] S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H.S. Kim, Y.W. Han, S.D. Kwon, Y.S. Oh, "Logic Failure Analysis 65/45nm Device Using RCI & Nano Scale Probe ", China, 16th IPFA (2009).
[82] K. Mizukoshi, T. Oyamada, A. Shimase, Y. Matsumoto, S. Yorisaki and T. Majima, "Fault Localization Using Electron Beam Current Absorbed in LSI Interconnects", Proc The 2004 International Meeting for Future of Electron Devices, Kansai, Kyoto, JAPAN, pp.391-392, (2004).

------------------------------------------------------------------------ 第 2 筆 ---------------------------------------------------------------------
系統識別號 U0026-0812200911512890
論文名稱(中文) 應用於高速系統晶片之球柵陣列封裝的訊號整合與非破壞分析
論文名稱(英文) Signal Integrity and Nondestructive Analysis of BGA Packaging for High Speed SOC Applications
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 94
學期 2
出版年 95
研究生(中文) 陳明坤
學號 n2891145
學位類別 博士
語文別 英文
口試日期 2006-06-20
論文頁數 87頁
口試委員 口試委員-毛齊武
口試委員-陳立軒
口試委員-羅錦興
口試委員-黃世杰
召集委員-黃有榕
指導教授-戴政祺
關鍵字(中) 電氣模型
時域反射分析儀
失敗分析
信號整合
高速系統晶片
球柵陣列
關鍵字(英) signal integrity (SI)
nondestructive analysis (NDA)
failure analysis (FA)
time domain relectrometry (TDR)
electrical model
high speed system-on-a-chip (HSSOC)
ball grid array (BGA)
學科別分類
中文摘要 隨著微電子應用的演進,複雜的元件能較高度的整合到系統晶片上,使其具有較高的速度、更多的功能與效能的增加。高速輸入輸出、矽智產與記憶體核心是高速系統晶片(High speed System-on-a-Chip; HSSOC)的三大主要元件,而高速系統晶片中有著高速輸入輸出界面將衍生出許多封裝與測試整合上的困難與挑戰。因此,在系統晶片佈局空間變得很小,提供系統的電壓值亦變小之下,封裝與測試上之信號完整度特性和失效分析對整個系統晶片發展結果的影響便十分重要。
本研究以量測技術為基礎進行球陣列封裝之信號完整性與故障非破壞分析,進而提供於高速系統晶片之應用。使用量測、建立模型與電路模擬的方法進行電氣特性與等效模型之建立,經由實際量測結果相互比較,建立適當的電子封裝等效電路模型。並進行信號完整性分析,探討球陣列封裝電子封裝電氣特性對高速數位系統晶片之影響。然後再使用一個端點開路治具加上時域反射分析儀檢視快速信號緣之時間間隔與反射電壓之參數,進行球柵陣列封裝過程的錯誤之非破壞分析。最後進行球柵陣列測試治具重複性之錯誤分析。





英文摘要 Microelectronic applications tend toward more complex components with higher integration at the system-on-a-chips (SoCs), higher speed, more functionality, and better performance. High speed I/Os, SIPs and memory cores are three key components in high speed SoC (HSSoC), which results in package and test integration challenges. These two issues make the package and test cost especially that related to package and test integration, one of the major costs in HSSoC development. How to increase the signal integrity of packaging and reduce the cost of high speed I/Os testing becomes an important subject so far as HSSoC development is major concerned. In order to succeed in the HSSoC products, much attention has been paid to the signal integrity (SI) and nondestructive analyses (NA) of the package interconnection. In order to succeed in the HSSoC products, much attention has been paid to the electrical model and failure analyses of the package interconnection. SI characterization and NA in the SOC package have caused significant challenges in BGA-type packaging design.
In this thesis, we propose applying a measurement technique to extracts high-speed FC-BGA packaging interconnects for signal integrity and analyze the interconnection of BGA packaging for the failure of packaging interconnections. Determining the real FC-BGA effects requires the measuring and the modeling by using TDR technique. Suitable and prompt modeling to the practical design and analysis will solve the measuring problem. HSPICE was applied to analyze the signal integrity of the package. To detect an interconnection failure in BGA packages, a nondestructive analysis system with TDR was developed. An open-end fixture (OEF) was employed to detect the rapid rise of edge signals from the package and to monitor them under the two parameters of time interval and reflection voltage. The test socket of BGA ia finally analyzed the various factors of contact effects in the production line.





論文目次 Abstract (Chinese) ------------------------------------------- Ⅰ
Abstract (English) ------------------------------------------- Ⅲ
Acknowledgment ----------------------------------------------- Ⅴ
Contents ----------------------------------------------------- Ⅵ
List of Figures ---------------------------------------------- Ⅷ
List of Tables ----------------------------------------------- ⅩⅠ
List of Abbreviations ---------------------------------------- ⅩⅢ
Chapter 1 Introduction --------------------------------------- 1
1.1 Basic building blocks of SOC ----------------------------- 2
1.2 Overview of electronic packaging for HSSOC --------------- 3
1.3 Signal integrity issues in the package level ------------- 5
1.4 Research motivations and novel contributions ------------- 8
1.5 Organization of the dissertation ------------------------- 10
Chapter 2 Lumped Model of FC-BGA Package --------------------- 11
2.1 TDR technical information -------------------------------- 12
2.2 Experimental sample and measurement setup ---------------- 16
2.2.1 Experimental sample ------------------------------------ 16
2.2.2 TDR measurement setup ---------------------------------- 17
2.3 FC-BGA equivalent lumped models -------------------------- 20
2.3.1 Single line extraction --------------------------------- 20
2.3.2 Even mode extraction ----------------------------------- 20
2.3.3 Odd mode extraction ------------------------------------ 24
2.4 Summary -------------------------------------------------- 25
Chapter 3 Modeling of Power Networks and SI Simulation ------- 26
3.1 Concept of signal-integrity issues ----------------------- 27
3.1.1 Noise sources in the packaging ------------------------- 27
3.1.2 Switching noise mechanism ------------------------------ 27
3.2 Electrical modeling power network ------------------------ 29
3.3 Examples SI simulations ---------------------------------- 34
3.3.1 Bandwidth limitation simulation ------------------------ 34
3.3.2 Simulation SSN ----------------------------------------- 39
3.3.3 Signal integrity simulation ---------------------------- 41
3.4 Summary -------------------------------------------------- 44
CHAPTER 4 Nondestructive Analysis of PBGA -------------------- 45
4.1 Proposed materials and methods --------------------------- 46
4.1.1 Package and substrate design --------------------------- 46
4.1.2 NDA measuring system------------------------------------ 46
4.1.3 Open-end fixture --------------------------------------- 47
4.1.4 System calibration ------------------------------------- 48
4.2 Fault analysis and verification -------------------------- 49
4.2.1 Complete open defect ----------------------------------- 50
4.2.2 Short defect ------------------------------------------- 53
4.3 Experimental results and discussion ---------------------- 54
4.4 Technique limitations ------------------------------------ 55
CHAPTER 5 Failure Analysis and Modeling of Test Socket ------- 56
5.1 Analyzing failure for socket ----------------------------- 56
5.1.1 Experiment test package and socket --------------------- 57
5.1.2 Analyzing failure for used-socket ---------------------- 59
5.2 Experimental results ------------------------------------- 61
5.3 Equivalent electrical model ------------------------------ 63
5.3.1 Operation behavior ------------------------------------- 63
5.3.2 Equivalent resistor model ------------------------------ 63
5.3.3 Equivalent inductance model ---------------------------- 66
5.3.4 Equivalent impedance model ----------------------------- 67
5.4 Operating reliability of socket -------------------------- 68
5.5 Summary -------------------------------------------------- 69
CHAPTER 6 Conclusions and Future Research Directions --------- 70
6.1 Conclusions ---------------------------------------------- 70
6.2 Future research directions ------------------------------- 72
Appendix ----------------------------------------------------- 73
Publications ------------------------------------------------- 77
Vita --------------------------------------------------------- 80
References --------------------------------------------------- 81
參考文獻 [1] C.Y. Chang and S.M. Sze, “ULSI Devices,” New York: Wiley Inter-Science, 2000.
[2] S. Bhanot, “Analog verification IP and the next stage in the evolution of system-on-chip,” Electronic Engineering Times, pp.18-20, 2005.
[3] J.A. Darringer, R.A. Bergamaschi, S. Bhattacharya, D. Brand, A. Herkersdorf, J.K. Morrell, I.I. Nair, P. Sagmeister and Y. Shin, “Early analysis tools for system-on-a-chip design,” IBM Journal of Research and Development, Vol. 46, No. 6, pp. 691-707, 2002.
[4] T.R. Bednar, P.H. Buffet, R.J. Darden, S.W. Gould and P.S. Zuchowski, “Issues and strategies for the physical design of system-on-a-chip ASICs,” IBM Journal of Research and Development, Vol. 46, No. 6, pp. 661-674, 2002.
[5] B. Young, “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages,” Prentice Hall, 2001.
[6] M. Nourani and A.R. Attarha, “Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips,” IEEE Trans. on Reliability, Vol. 51, No. 4, pp. 494-504, 2002.
[7] D. Edenfeld, A.B. Kahng, M. Rodgers and Y. Zorian, “2001 technology roadmap for semiconductors,” Computer, Vol. 37, Issue 1, pp. 47-56, 2004.
[8] M. Nourani and A.R. Attarha, “Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips,” IEEE Trans. on Reliability, Vol. 51, No. 4, pp. 494-504, 2002.
[9] “INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS- 2003 EDITION, Assembly and Packaging,” http://public.itrs.net/, 2003.
[10] S.P. Beaumont, “The SOC challenge,” Electronics & Communication Engineering Journal, Vol. 13, Issue 6, pp. 234-235, 2001.
[11] H. Chang et al, “Surviving the SOC Revolution,” Kluwer Academic Publishers, 1999.
[12] H.B. Bakoglu, “Interconnections, and Packaging for VLSI Circuits,” Addison-Wesley Publishing Company, Inc., 1990.
[13] “PCI Express Base Specification Revision 1.0,” PCISIG, 2002.
[14] “RapidIO Physical Layer 8/16 LP-LVDS AC Specification,” RapidIO Technical Working Group, pp. IV-95-IV-108, 2001.
[15] F. Sam, “RapidIO: The Embedded System Interconnect,” John Wiley & Sons Ltd, 2005.
[16] “Hypertransport I/O Link Specification Revision 1.03,” Hypertransport Technology Consortium, pp. 187-193, 2001.
[17] B. Wang, A. Kuo, T. Farahmand, A. Ivanov, B. Yong Cho and S. Tabatabaei, “A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices,” Journal of Electronic Testing: Theory and Applications 21, pp. 621–630, 2005.
[18] R.R. Tummala, “Microelectronics Packaging Handbook, 2nd-Edition,” London, U.K.: Chapman and Hall, 1997.
[19] T.R. Bednar, P.H. Buffet, R.J. Darden, S.W. Gould and P.S. Zuchowski, “Issues and strategies for the physical design of system-on-a-chip ASICs,” IBM Journal of Research and Development, Vol. 46, No. 6, pp. 661-674, 2002.
[20] W. Wolf, “Modern VLSI Design: System-on-Chip Design, 3rd-Edition,” Prentice Hall, 2002.
[21] J.H. Lau, “Ball Grid Array Technology,” McGraw-Hill, New York, 1995.
[22] J.H. Lau, “Flip Chip Technology,” McGraw-Hill, New York, 1996.
[23] G. B. Kromann, D. Gerke and W. Huang, “Motorola's power PC603 and Power PC 604 Risc Micro processor,” in Proc. C4/Ceramic-Ball-Grid Array Interconnect Technology Conference, 45th ECTC/IEEE, 1995.
[24] M. Mita, G. Murakami, T. Kumakura and F. Kashiwabara, “Manufacturing process for combination lead frame/TAB BGA,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part C, Vol. 21, No. 3, pp. 204-210, 1998.
[25] J.H. Lau, “Low Cost Flip Chip Technologies,” McGraw-Hill Inc., New York, 2000.
[26] H.W. Johnson and M. Graham, “High Speed Signal Propagation: Advanced Black Magic,” Prentice Hall PTR, NJ, 2003.
[27] S. Kronsowski and A. Helland, “Electronic Packaging of High Speed Circuitry,” McGraw Hill, 1997.
[28] W.J. Howard and M. Graham, “High-Speed Signal Propagation-Advanced Black Magic,” Prentice Hall, 2003.
[29] “INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS- 2005 EDITION, Assembly and Packaging,” http://public.itrs.net/, 2005.
[30] T.S. Horng, S.M. Wu, A. Tseng and H.H. Huang, “Electrical modeling of enhanced ball grid array packages using coupled transmission lines,” Electronics Letters, Vol. 35, Issue 18, pp. 1567-1569, 1999.
[31] T.S. Horng, S.M. Wu, J.Y. Li, C.T. Chiu and C.P. Hung, “Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages,” Electronic Components and Technology Conference, pp. 439-444, 2000.
[32] T.S. Horng, S.M. Wu and C. Shih, “Electrical modeling of RFIC packages up to 12 GHz,” Electronic Components and Technology Conference, pp. 867-712, 1999.
[33] D.E. Carlton, K.R. Gleason, R. Hopkins, K. Jones, K. Noonan and E.W. Strid, “Accurate measurement of high-speed package and interconnect parasitics,” IEEE Custom Integrated Circuit Conference, pp. 23.3.1-23.3.7, 1988.
[34] R. Ito, R.W. Jackson and T. Hongsmatip, “Modeling of interconnections and isolation within a multilayered ball grid array package,” IEEE Trans. on Microwave Theory and Techniques, Vol. 47, Issue 9, pp. 1819-1825, 1999.
[35] J. Jeong, S. Nam, Y.S. Shin, Y.S. Kim and J. Jeong, “Electrical characterization of ball grid array packages from S-parameter measurements below 500 MHz,” IEEE Trans. on Advanced Packaging, Vol. 22, Issue 3, pp. 343-347, 1999.
[36] B. Young and A.K. Sparkman, “Measurement of package inductance and capacitance matrices,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, part B, Vol. 19, pp. 225–229, 1996.
[37] T. Hamano and Y. Ikemoto, “Electrical characterization of a 500 MHz frequency EBGA package,” IEEE Trans. on Advanced Packaging, Vol. 24, Issue 4, pp. 534-541, 2001.
[38] J.H. Lau and T.Y. Chou, “Electrical design of a cost-effective thermal enhanced plastic ball grid array package-NuBGA,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 21, Issue 1, pp. 35-42, 1998.
[39] J.M. John, B. Janko and V.K. Tripathi, “Time-domain characterization and circuit Modeling of a multilayer ceramic package,” IEEE Trans. on Components, Packaging, and Manufacturing Techno logy –PART B, vol. 19, pp. 48-56, 1996.
[40] L.T. Huang, G.A. Rinne and I. Turlik, “An extended time-domain network analysis measurement technique,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, vol. 18, pp. 375-380, 1995.
[41] S. Pannala, A. Haridass and M. Swaminathan, “Parameters extraction and electrical characterization of high density connector using time domain measurements,” IEEE Trans. on Advanced Packaging, vol. 22, pp. 32-39, 1999.
[42] D. Tom, M. Luc and Z. De, “Calibration and Normalization of Time Domain Network Analyzer Measurement,” IEEE Trans. on Microwave and Techniques, Vol. 42, No. 4, pp. 580-589, 1994.
[43] M.K. Chen, C.C. Tai, Y.J. Huang and S.L. Fu, “Electrical Modeling of FC-BGA for High Speed Package Applications,” 2004 International Conference on Electronics Packaging (ICEP), Dai-ichi Hotel Tokyo Seafort, Tennoz Isle, Tokyo, Japan. pp. 319-324, 2004.
[44] “TDR Tools in Modeling Interconnects and Packages,” Tektronix apply note 85W-8885-0, 1993.
[45] P.I. Somlo and J.D. Hunter, “Microwave Impedance Measurement,” Peter Peregrinus Ltd., London, UK, 1985.
[46] “User's Guide-Agilent 54753A and 54754A TDR Plug-in Modules,” Agilent Technologies Publication Number 54753-97015, 2000.
[47] T.D. Moore, D. Vanderstraeten and P. Forsell, “Determination of BGA Structural Defects and Solder Joint Defects by 3D x-ray Laminography,” in IEEE Proceeding of 8th IPFA, pp. 146-150, 2001.
[48] M. Ohring, “Reliability and Failure of Electronic Material and Device,” Academic Press, San Diego, 1998.
[49] D.M. Thomas and L.J. John, “Failure Analysis and Stress Simulation in Small Multichip BGAs,” IEEE Trans. on Advanced Packaging, 24, pp. 216-223, 2001.
[50] T.D. Moore, D. Vanderstraeten and P.M. Forssell, “Three-dimensional x-ray laminography as a tool for detection and characterization of BGA package defects,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 25, No. 2, pp. 224-229, 2002.
[51] P.I. Somlo and D.L. Hollway, “Microwave locating reflectometer,” Electronic Letter, 5, pp. 468–469, 1969.
[52] L. Philen, I.A. White, J.F. Kuhl and S.C. Mettler, “Single-mode fiber OTDR: Experiment and theory,” IEEE Trans. on Microwave Theory and Technology, MTT-30, pp. 1487–1496, 1982.
[53] “Time Domain Reflectometry Theory,” Agilent Application Note 1304-2, Agilent Technologies website: http:www.agilent.com.
[54] “Electronic Package Failure Analysis Using TDR,” TDR System Application Note, URL: http://www.tdasystems.com.
[55] O. Charles and L. Craig, “Reflectometry Techniques Aid IC Failure Analysis,” Test & Measurement World, 2000, URL: http://www.reed-electronics.com/tmworld.
[56] M.K. Chen, C.C. Tai, Y.J. Huang and I.C. Wu, “Failure analysis of BGA package by a TDR approach,” in Proc. IEEE International symposium Electronic Material Packaging, pp. 112-116, 2002.
[57] C. Lihong, H.B. Chong, J.M. Chin and R.N. Master, “Non-destructive analysis on flip chip package with TDR and SQUID,” IEEE in Conference Electronic Packaging Technology, pp. 50-55, 2002.
[58] A. K. Goel, “High-Speed VLSI Interconnection Modeling, Analysis and Simulation,” Wiley-Interscience, 1994.
[59] D.L. Smith and A.S. Alimonda, “A new flip-chip technology for high-density packaging,” Electronic Components and Technology Conference, pp. 1069-1073, 1996.
[60] T.W. Goodman, H. Fujita, Y. Murakami and A.T. Murphy, “High speed electrical characterization and simulation of a pin grid array package,” IEEE Trans. On Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 18, Issue 1, pp. 163-167, 1995.
[61] S.H. Hall, G.W. Hall and J.A. Mccall, “High-Speed Digital System Design-A Handbook of Interconnect Theory and Design Practices,” John Wiley & Publication, 2000.
[62] Y.C. Chen, P. Harms, R. Mittra and W.T. Beyene, “An FDTD-Touchstone hybrid technique for equivalent circuit modeling of SOP electronic packages,” IEEE Trans. on Microwave Theory and Techniques, Vol. 45, Issue 10, pp.1911-1918, 1997.
[63] “IConnectR Version 3.0 User Manual,” 2003 TDA Systems, Inc.
[64] D.A. Smolyansky and S.D. Corey, “Computing Self and Mutual Capacitance and Inductance Using Even and Odd TDR Measurement,” IEEE conference of Electrical Performance of Electronic Packaging, pp. 117-122, 2002.
[65] “Agilent N1020A-K05 TDR Calibration Substrate Product Overview,” Agilent technologies Application Note N1020A-K05.
[66] T. Dhaene, L. Martens and D. Zutter, “Calibration and Normalization of Time Domain Network Analyzer Measurement,” IEEE Trans. on Microwave and Techniques, Vol. 42, No. 4, pp. 580-589, 1994.
[67] “User's Guide-Agilent 54753A and 54754A TDR Plug-in Modules,” Agilent Technologies Publication Number 54753-97015, 2000.
[68] SIA, “International Technology Roadmap for Semiconductors,” www.semichips.org, 2004.
[69] J.G. Yook, L.P.B. Katechi, K.A. Sakallah, R.S. Martin, L. Huang and T.A. Schreyer, “Application of system-level EM modeling to high-speed digital IC packages and PCB’s,” IEEE Trans. Microwave Theory and Technology, Vol. 45 , pp. 1847-1856, 1997.
[70] A.R. Djordjevic and T.K. Sarkar, “An investigation of delta-I noise on integrated circuits,” IEEE Trans. on Electromagnet Compatibility, Vol. 35, pp. 134-147, 1993.
[71] N. Na, J. Choi, M. Swaminathan, J. P. Libous and D. P. O’Connor, “Modeling and simulation of core switching noise for ASICs,” IEEE Trans. on Advanced Packaging, Vol. 25, pp. 1-4, 2002.
[72] J.P. Libous and D.P. O’Connor, “Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA,” IEEE Trans. on Components, Packaging, and Manufacturing Technology B, Vol. 20, pp. 266–271, 1997.
[73] B. McCredie and W. Becker, “Modeling, measurement and simulation of simultaneous switching noise,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 19, pp. 461–472, 1996.
[74] G. Katopis, B. Singh, W. Becker and H. Smith, “Delta-I modeling approximation for single chip modules,” in Proc. IEEE 5th Topical Meeting Electrical Performance Electronic Packaging, pp. 111–113, 1996.
[75] H. Chen and J. Neely, “Interconnect and circuit modeling techniques for full-chip power supply noise analysis,” IEEE Trans. on Components, Packaging, and Manufacturing Technology B, Vol. 21, pp. 209–215, 1998.
[76] J. Darnauer, D. Chengson, B. Schmidt, E. Priest, D.A. Hanson and W.G. Petefish, “Electrical evaluation of flip-chip package alternatives for next generation microprocessors,” IEEE Trans. on Advanced Packaging, Vol. 22, Issue 3, pp. 407-415, 1999.
[77] P. Anjay, D. Blaauw, V. Zoloto, S. Sundareswaran and R. Panda, “Vectorless analysis of supply noise induced delay variation,” International Conference on ICCAD-2003, 9-13, pp. 184-191, 2003.
[78] T. Chang, P.H. Cheng, H.C. Huang and R.S. Lee, “Parasitic characteristics of BGA packages,” IEEE Symposium on IC/Package Design Integration Proceedings, pp. 124-129, 1998.
[79] LabViewTM, URL: http://www.ni.com/labview/.
[80] L. Martens, “High-frequency Characterization of Electric Packaging,” Kluwer Academic, pp. 63, 1998.
[81] Q. Qiao, M.H. Gordon, W.F. Schmidt, L. Li, S.S. Ang and B. Huang, “Development of a Wafer-Level Burn-In Test Socket for Fine-Pitch BGA Interconnect,” Proceedings. 50th Electronic Components and Technology Conference, pp. 1147-1151, 2000.
[82] S. Chowdhury, M. Ahmadi, G.A. Jullien and W.C. Miller, “A MEMS socket system for high density SOC interconnection,” IEEE International Symposium on Circuits and Systems, 2002. ISCAS 2002. Vol. 1, pp.I-657-I-660, 2002.
[83] D.Y. Shih, P. Lauro, K. Fogel, B. Beaman, Y.H. Liao and J. Hedrick, “New ball grid array module test sockets,” Proceedings 46th Electronic Components and Technology Conference, pp. 467-470, May 1996.
[84] B. Chan and P. Singh, “BGA sockets-a dendritic solution,” IEEE 46th Electronic Components and Technology Conference, pp. 460–466, 1996.
[85] W. Liu, M. Pecht and R. Martens, “IC Component Sockets: Applications and Challenges,” IMAPS, Vol. 24, No. 1, First Quarter, pp. 61-67, 2001.
[86] M.K. Chen, C.C. Tai, Y.J. Huang and S. Fang, “Electrical Characterization of BGA Test Socket for High-Speed Applications,” The 4th International Symposium on Electronic Materials and Packaging 2002, Kaohsiung, Taiwan, pp. 123-126, 2002.
[87] R. Knudsen, “Good Contact Design Improves Test Performance in BGA/CSP Applications,” Chip Scale review, 1998.
[88] J.G. Zhang and X.M. Wen, “The Effect of Dust Contamination on Electric Contacts,” IEEE Trans. on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-9, No 1, pp. 53-58, 1986.
[89] L. Boyer, F. Houze and S. Noel, “Electrical and Physical Modeling of Contact defect Due to Fretting,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 17, No. 1, pp. 134-140, 1994.
[90] J. Xie, C. Hillman, P. Sandborn, M. G. Pecht, A. Hassanzadeh and D. DeDonato, “Assessing the Operating Reliability of Land Grid Array Elastomer Sockets,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 23, No. 1, pp. 171-176, 2000.
[91] R. Holm, “Electric Contacts-Theory and Applications,” Springer-Verlag, Heidelberg, 2000.
[92] R. Mroczkowski, “Electronic Connector Handbook: Theory and Applications,” McGraw-Hill, New York, 1998.
[93] M. R. Pinnel and K.F. Bradford, “Influence of Some Geometric Factors on Contact Resistance Probe Measurements,” IEEE Trans. on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-33, No. 1, pp. 159-165, 1980.
[94] M.F. Caggiano, E. Barkley, M. Sun and J.T. Kleban, “Electrical modeling of the chip scale ball grid array package at radio frequencies,” Microelectronics Journal, Vol. 31, pp. 701-709, 2000.
[95] J.D. Kraus and D.A. Fleisch, “Electromagnetic with application-fifth Edition,” McGraw-Hill, 1999.
[96] B.W. Johnson, “Design and Analysis of Fault-Tolerant Digital Systems,” Addiison-Wesley Publishing Company, pp. 185-199, 1989.
[97] T.Granberg, “Handbook of Digital Techniques for High-Speed Design: Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling, and Simulation to Ensure Signal Integrity,” Prentice Hall PTR, United States of America, 2005.

------------------------------------------------------------------------ 第 3 筆 ---------------------------------------------------------------------
系統識別號 U0026-0812200911533959
論文名稱(中文) 互補式金氧半導體積體電路故障分析技術比較
論文名稱(英文) The Comparison of Failure Analysis Technologies in Complementary Metal Oxide Semiconductor Integrated Circuit
校院名稱 成功大學
系所名稱(中) 電機工程學系專班
系所名稱(英) Department of Electrical Engineering (on the job class)
學年度 94
學期 2
出版年 95
研究生(中文) 洪惠全
學號 n2792101
學位類別 碩士
語文別 英文
口試日期 2006-05-30
論文頁數 82頁
口試委員 口試委員-陳貞夙
口試委員-劉全璞
口試委員-陳志方
指導教授-張守進
口試委員-林志賢
關鍵字(中) 被動式電壓對比
微光偵測術
熱束產生電流變化術
互補式金氧半導體
積體電路
液晶偵熱術
故障分析
螢光微熱偵測術
關鍵字(英) Failure Analysis
Passive voltage contrast
Fluorescent micro-thermal microscopy
Integrated Circuit
Thermal beam induced current variation
Liquid crystal microscopy
Emission microscopy
Complementary Metal Oxide Semiconductor
學科別分類
中文摘要   半導體工業開始於 20 世紀下半, 並迅速成長. 整個業界的產能很快在 20 世紀末超過市場的消耗量. 產品的生命週期也變得更短壓縮到獲利. 特別是產業垂直分工, 更降低半導體工業界的進入門檻, 導致上市時程成為關鍵. 目前在電腦的輔助下可以很精準的控制設計和生產時程, 但是第一批的良率常常非常低. 導致上市時程延長, 減低獲利, 甚至於賠錢. 低良率可能肇因於設計, 製造或兩者的相互作用並且形成高阻值或漏電. 故障分析成找尋高阻值或漏電的成因在良率提升上扮演相當重要的角色.

  故障分析的技術如液晶偵熱術 (liquid crystal microscopy), 螢光微熱偵測術 (fluorescent micro-thermal microscopy), 微光偵測術 (emission microscopy), 熱束產生電流變化術 (thermal beam induced current variation), 和被動式電壓對比 (passive voltage contrast) 被用來定位故障位置, 本論文探討數個真實案例的故障機制和找到的缺陷, 以比較各故障分析術的優缺點.

英文摘要   The industry of integrated circuit (IC) semiconductor started at the middle of twenty century and grows fast at the second half century. The capacity of the IC industry exceeds the consumption of the market at the end of twenty century. The cycle time of a product getting shorter compresses the profile. Especially the vertical division of semiconductor industry decreases the barrier of entry. The time-to-market becomes critical to the profit. The design and manufacturing period with computer-aided automation are well controlled and very precisely, but yield rate of the first cut always get low yield. This violently extends the time-to-market, reduces profit or even losses money. The low yield may comes from design, manufacturing or interaction of both and almost induced by high resistance or leakage circuit. Failure analysis to identify the cause of high resistance and leakage plays a significant role to improve the yield.

  The failure analysis technologies, liquid crystal microscopy, fluorescent micro-thermal microscopy, emission microscopy, thermal beam induced current variation, and passive voltage contrast are used to locate the failure site. Several real cases are demonstrated in this thesis to discuss the possible failure mechanism and find out the defect, in order to compare these failure analysis technologies.

論文目次 Abstract 1
1. Introduction 2
History of IC Industry and Failure Analysis 2
2. Behavior Of Failure: 5
2.1. Heat Generation 5
2.2. Light Emission 7
3. Failure Site Localization 8
3.1. Liquid Crystal Microscopy 8
i. Theory 8
ii. System 10
iii. Operating Procedure 11
Case1, Power Short 11
Case2, Functional Test Failure 13
iv. Advantage 15
v. Limitation 15
3.2. Fluorescent Micro-thermal Microscopy 16
i. Theory 16
ii. System 17
iii. Operating Procedure 18
Case1, Metal Test Key Short 19
Case2, Memory Functional Test Failure 21
vi. Advantage 22
vii. Limitation 23
3.3. Thermal Beam Induced Current Variation 23
i. Theory 23
ii. Seebeck Effect 25
iii. Application 27
iv. System 29
v. Case1, Test Structure Leakage 31
vi. Case2, Metal Inter-connector VIA High Resistance 33
vii. Case3, Seebeck Effect on N-doped, P-doped Contact 34
viii. Case4, Functional Failure 36
ix. Case5, Gate Floating CMOS 37
x. Case6, Scan Function Failure 39
xi. Case7, Normal Functional Failure 40
viii. Advantage 41
ix. Limitation 41
3.4. Emission Microscopy 41
i. Theory 41
ii. Hot carrier emission 41
iii. Combination Emission 44
iv. Blackbody Radiation 45
v. System 48
vi. Operating Procedure 50
vii. Case1, Functional Failure 50
viii. Case2, Self-functional Test Failure 53
ix. Case3, JEDEC Functional Test Failure 57
x. Advantage 59
xi. Limitation 60
3.5. Passive Voltage Contrast: 60
i. Basic Structure of SEM 60
ii. Theory 62
iii. Secondary Electron Yield 64
iv. Passive Voltage Contrast 67
v. Passive Voltage Contrast in CMOS IC 69
vi. Case1, Embedded Memory Failure 71
vii. Case2, Functional Failure 72
viii. Case3, Continuity Failure 73
xii. Advantage 74
xiii. Limitation 74
4. Summary and future work 75
Reference 76
參考文獻 References:
1. TI web home, Jack St. Clair Kilby , “The Chip that Jack Built Changed the World”.
2. Press released at web of Samsung press cent on June 23 2005, “SAMSUNG First to Produce 1 Gb DDR2 Dynamic Random-Access Memory (DRAM) Using 90 Nanometer Process Technology”.
3. ISSCC 2003,G. MOORE “No exponential is forever, but ‘forever’ can be delayed”.
4. Source: TSMC Market Research Program estimates, Company Reports, IC insights, April 2005.
5. Source: IC Insights March 2005.
6. T. Williams, R.Kapur,M Mercer, R. Dennard, and W. Maly, “IDDQ Testing for High Performance CMOS- The Next Ten Years”, Proceedings of the European Design and Test Conference ( EDTC’96), 1996, pp.578.
7. James Lin, “ Challenges for SoC Design in Very Deep Submicron Technology”, National Semiconductor, ISSS2003, Oct. 2003.
8. Manish P. Pagey, Hot-carrier reliability simulation in aggressively scaled mos transistors. 2003, P14-P20.
9. S.Z. Sze, , John Wiley and Sons, Physics of Semiconductor Devices, Wiley, New York, 1981, pp14.
10. M. P. Godlewski, C. R. Baraona, and H. Brandhorst, “ Low-high junction theory applied to solar cells,” in Proceeding IEEE Photovol. Spec. Conference, 1973, pp.40-49.
11. Steven Frank, Wilson Tan, and John West,”Electrical Characterization” in “ Failure Analysis of Integrated Circuits: Tools and Techniques”, Kluwer Academic Publishers, 1999, pp.13.
12. S. Khandekar, K. S. Willis “Liquid Crystal Microscopy”, Electronics Failure Analysis - Seminar Referen ce, p. 139 ASM International 1998.
13. Adam K. Fontecchio, “Multiplexing studies ofholographically-formed polyer dispersed liquid crystals: morphology, structure, and device applications”, May 2003, pp 108.
14. A. Csendes, V.Székely, M. Kerecsen-Rencz : Thermal mapping with liquid crystal method, Microelectronic Engineering V.31, pp.281-290 (1996).
15. G. Aszódi, J. Szabóné, I. Jánossy, V.Székely: High resolution thermal mapping of microstructures using nematic liquid crystals, Solid-State Electronics, V.24,No.12. pp.1127-1133 (1981).
16. Kolodner, P., and A. Tyson. 1982. Microscopic fluorescent imaging of surface temperature profiles with 0.01°C resolution. Appl. Phys. Lett. 40:782-784.
17. Kolodner, P., and A. Tyson. 1983. Remote thermal imaging with 0.7-micron spatial resolution using temperature-dependent fluorescent thin films. Appl. Phys. Lett. 42:117-119.
18. Barton, D. L. 1994. Fluorescent microthermographic imaging. Proc. Int. Symp. Test. Failure Anal. 20:13-18.
19. Crosby, G. A., R. E. Whan, and R. M. Alire. 1961. Intramolecular energy transfer in rare earth chelates. Role of the triplet state. J. Chem. Phys. 34:743-748.
20. Winston, H., O. J. Marsh, C. K. Suzuki, and C. L. Telk. 1963. Fluorescence of europium thenoyltrifluoroacetonate. I. Evaluation of laser threshold parameters. J. Chem. Phys. 39:267-271.
21. Bhaumik, M. L. 1964. Quenching and temperature dependence of fluorescence in rare earth chelates. J. Chem. Phys. 40:3711-3715.
22. Runzi Chang, Member, IEEE, and Costas J. Spanos, Fellow, IEEE. “Dishing-Radius Model of Cpooer CMP Dishing Effects”, IEEE Transactions on Semiconductor Manufacturing, vol. 18, No. 2, May 2005.
23. Mark Pitt Robeson, “Temperature Dependence of Conductivity in a Metal, a. Semiconductor, and a Superconductor”, http://www.phys.vt.edu, 2005.
24. B F Hann, “An approach to Electrical Conductivity in Solids”, Physics Education, IOP Electronic Journals, 4 pp.207-211, 1969.
25. Thomas Johann Seebeck (1770-1831), ERIC Weisstein’s World of Biography, Wolfram Research, http://scienceworld.wolfram.com
26. Baltes, H., Moser, D., Freidemanm, V., “ Thermoelectric Microsensors and Mechanical Sensors,” Sensors vol 7 ed. Bau, H.H., de Rooji, B., Kleck, VCH Verlag, Weinheim, pp.13-55,1994.
27. S.M. Sze, “ Semiconductor Sensors”, New York: Wiley, 1994.
28. Jaeggi, D. “ Thermal Converters by CMOS Technology,” Ph D. Thesis, Zurich: Physical Electronics Laboratory. 1996.
29. Dana Tesdale, “ Solid Propellant Microrockets”, Master Thesis, EE and CS, University of California.S
30. Baur, M. Kicherer, "1.55 um and 1.3 um DFB lasers with electro absorption modulators for high-speed transmission systems", Second Joint Symposium on Opto- and Microelectronic Devices and Circuits (SODC) 2002, Stuttgart, Mar.2002.
31. Warrant J, Smith, “ The Design of Optical Systems”, McGraw-Hill, 3rd BK & CD edition, July 2000.
32. Michael A. Ferenczi, “Light Microscopy - Beyond the limits of optical resolution”, National Institute for Medical Research, 1997.
33. S. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, New York, 1981. Jellison, Jr., G. E. and F. A. Modine, Applied Physics Letter 41, 2, pp. 180 –182, 1982. Hand book of Optical Constants, E. Palik, Ed., Academic Press, 1985.
34. S. J. Bennett, “The thermal expansion of copper between 300 and 700K”, Journal Physics D: Applied Physics 11 pp. 777-780,1978.
35. T. Williams, R.Kapur,M Mercer, R. Dennard, and W. Maly, “IDDQ Testing for High Performance CMOS- The Next Ten Years”, Proceedings of the European Design and Test Conference ( EDTC’96), 1996, pp.578.
36. Donald A. Neamen, “Semiconductor Physics & Devices Basic Principles“, IRWIN, second edition, ISBN 0-256-20869-7, 1997.
37. Manish P. Pagey, Hot-carrier reliability simulation in aggressively scaled mos transistors. 2003, P14-P20.
38. S. Sze, Physics of Semiconductor Devices, John Wiley and Sons, New York, 1981.
39. A. Duncan, U. Ravaioli, and J. Jakumeit, “ Full-Band Mote-Carlo Investigation of Hot-Carrier Trends in the Scaling of Metal-Oxide-Semiconductor Ffield-Effect Transistors”, IEEE Transactions on Electorn Devices, vol. 45, no. 4, P867, Apr. 1998.
40. R. Hulfachor, K. Kim, M. Littlejohn, and C. Osburn, “Comparative Analysis of Hot Electron Injection and Induced Device Degradation in Scaled 0.1um SOI n-MOSFETs using Monte Carlo Simulation”, IEEE Electron Device Letters, vol. 17, no. 2, P53, Feb. 1996.
41. J. Higman, K. Hess, C. Hwang, and R. Dutton, “ Coupled Monte Carlo-Drift Diffusion Analysis of Hot-Electron Effects in MOSFETs”, IEEE Transactions on Electron Devices, vol. 36, no. 5, pp. 930, May 1989.
42. S. Sze, Physics of Semiconductor Devices, John Wiley and Sons, New York, 1981.
43. LenWB, Liu YY, Phang JCH Chan DSH, “ Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Device”, Procedure International Symposium for Testing and Failure Analysis, pp311-316, 2003.
44. Maria Eloisa Castagna et al., "High Efficiency Light Emitting Devices in Silicon", Materials Science and Engineering B, 15 December 2003, pp. 83-90.
45 J. C. White and J. G .Smith, “Observation of carrier densities in silicon devices by infrared emission”, Journal of Physics E: Scientific Instruments 10 pp. 817-825, 1977
46. E.I. Cole Jr., P. Tangyunyong, D.A. Benson, D.L. Barton, “TIVA and SEI Developments for Enhanced Front and Backside Interconnection Failure Analysis”, Proceedings of the 10th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 1999, pp991-996.
47. G. Deboy and J. Kolzer, “Fundamentals of light emission from silicon devices”, Semiconductor Science and Technology 9, pp. 1017-1032, 1994.
48. Daniel L. Barton, Edward I. Cole Jr., Karoline Berhard-Hofer, “Flip-Chip and Backside Sample Preparation Techniques“, Microelectronics Failure Analysis, Oct 2004, pp 43 –49.
49. J. Colvin, “BGA and advanced package Wire to Wire bonding for Backside emission microscopy”, International Symposium Testing and Failure Analysis proceedings, pp.365-375, 1999.
50. Planck, Max, "On the Law of Distribution of Energy in the Normal Spectrum (http://dbhs.wvusd.k12.ca.us/webdocs/Chem-History/Planck-1901/ Planck-1901.html)". Annalen der Physik, vol. 4, p. 553 ff (1901).
51. K. SCHRODER, “ Advanced MOS Devices”, Readings, Massachusets, Addison-Wesley Publication. Co. 1987.
52. Chris McFee, “Type of Noise in A CCD”, CCD Group, Detector Physics Group, Mullard Space Science Laboratory , July, 2005.
53. D.E. Groom et al., “Quantum efficiency of a back-illuminated CCD imager: an optical approach,” inProc. SPIE, 3649, pp. 80–90, 1999.
54. S.E. Holland, D.E. Groom, N.P. Palaio, R.J. Stover, and M. Wei, “Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon,” IEEE. Trans. Elec. Dev., 50, pp. 225–238, 2003
55. W. Maly, C. Ouyang, S. Ghosh, and S. Maturi, “Detection of an antenna effect in VLSI designs”, IEEE internal Symposium on Defect and Fault Tolerance in VLSI System, pp.86-94, Nov. 1996.
56. S. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, New York, 1981.
57. David P. Vallett. "IC Failure Analysis: The Importance of Test and Diagnostics," IEEE Design and Test of Computers, vol. 14, no. 3, pp. 76-82, July-September, 1997.
58. Allen R. Sampson, “Scanning Electron Microscopy”, Advanced Research Systems, December 2, 1996.
59. Anderson CA, ed., 1973, Microprobe Analysis, John Wiley & Sons, pp 571.
60. James H. Wittke, “Electron Microprobe”, Electron Microprobe Laboratory & Meteoritics Laboratory, Bilby Research Center, Northern Arizona University.
61. Brian Robertson, Xingzhong Li, QiangMin Wei, “Central Facility for Electron Microscopy”, Center for Materials Research and Analysis University of Nebraska-Lincoln.
62. Aphrodite Indares, Michael Shaffer, “Specimen Interaction and Information Generated with Electron Beam Instruments”, Electron Probe,2, pp 9-11, 2005.
63. Goldstein JI, Newbury DE, Echlin P, Joy DC, Fiori C & Lifshin E, “Scanning Electron Microscopy and X-ray Microanalysis”, Plenum Press, pp. 673, 1981.
64. Goldstein JI, Newbury DE, Echlin P, Joy DC, Romig, A.D. Jr., Eric L., 1992, “ Scanning Electron Microscopy and XX-ray Microanalysis”, A text for biologists, materials scientists, and geologist. 2nd edition, Plenum Press, New York.
65. Wittry, DB, 1973, Applications of the electron microprobe to solid- state electronics, in Anderson, C.A., ed., Microprobe Analysis, Wiley, 123-187.
66. Vick Guo, “ Introduction to Electron Microscopy and Microanalysis”, Oct. 21, 2005, pp.7-11.
67. J.A. Wert, “SCANNING ELECTRON MICROSCOPY”, chapter 7, Laboratory Manual Chapters, Department of Materials Science and Engineering, University of Virginia, Charlottesville, VA 22903.
68. I.M. Watt, “The Principle and Practice of Electron Microscopy”, Cambridge University Press, London 1985, pp.67.
69. K. S. Sim, J. T. L. Thong, J. C. H. Phang, “Effect of Shot Noise and Secondary Emission Noise in Scanning Electron Microscope Images”, The Journal of Scanning Microscopies, SCANNING VOL. 26, pp.36–40, 2004.
70. H. Seiler, “ Secondary Electron Emission in the Scanning Electron Microscope”, Journal of Applied Physics, 54, pp. R1-R8, 1983.
71. Newbury, D.E., Joy, D.C., Echlin, P., Fiori, C.E., and Goldstein, J.I. 1986. Advanced Scanning Electron Microscopy and X-Ray Microanalysis. Plenum, New York.
72. Gabriel, B.L. 1985. SEM: A Users Manual for Materials Science. American Society for Metals, Menlo Park, Ohio.
73. Newbury, D.E., Joy, D.C., Echlin, P., Fiori, C.E., and Goldstein, J.I. 1986. Advanced Scanning Electron Microscopy and X-Ray Microanalysis. Plenum, New York.
74. V. Baglin, J. Bojko, O. Grobner, B. Henrist, N. Hilleret, C. Scheuerlein, M. Taborelli CERN, Geneva, Switcerland, “The Secondary Electron Yield of Technical Materials and its Variation with Surface Treatments”,Proceedings of EPAC, Vienna, Astria, 2000.
75. Suszcynsky, D.M., Borovsky, J.E., and Goertz, C.K., “ Secondary Electron Yields of Solar System Ices”, Advanced Space Resolution. !3, pp.183-187.
76. ” Th Science of Static Electricity”, The Bakken Library and Musium.
77. Jbara O., Belhaj M., Odof S., Msellak K., Rau E. I., Andrianov M. V.,” Surface Potential Measurements of Electron-Irradiated Insulators using Backscattered and Secondary Electron Spectra from an Electrostatic Toroidal Spectrometer Adapted for Scanning Electron Microscope Applications”, Review Of Scientific Instruments, Vol 72, Iss 3, 2001.
78. S. Sze, Physics of Semiconductor Devices, John Wiley and Sons, New York, 1981.

------------------------------------------------------------------------ 第 4 筆 ---------------------------------------------------------------------
系統識別號 U0026-0812200915142933
論文名稱(中文) 比對線上缺陷檢驗與晶圓測試以改進奈米 CMOS製程良率提昇程序的時效與成本之 研究
論文名稱(英文) Enhancement of Nano CMOS Technology Yield Improving Cycle Time and Cost with Matching In-line Defect Inspection and Wafer Testing
校院名稱 成功大學
系所名稱(中) 電機工程學系專班
系所名稱(英) Department of Electrical Engineering (on the job class)
學年度 97
學期 2
出版年 98
研究生(中文) 何青陽
學號 n2795127
學位類別 碩士
語文別 英文
口試日期 2009-06-26
論文頁數 146頁
口試委員 指導教授-方炎坤
指導教授-謝明得
口試委員-謝明君
口試委員-陳鉅冺
口試委員-管鴻
關鍵字(中) none
關鍵字(英) Graphic Data System
Defect Density
Physical Failure Analysis
Turn Around Time
Front-End-Of-Line
Critical Dimension
Graphical User Interface
Configurable Logic Blocks
Electronic Design Automation
Design For Testability
Automatic Test Pattern Generator
Electron-Beam Inspection
Standard Operation Procedure
Back-End-Of-Line
Device Under Test
Field Programmable Gate Array
學科別分類
中文摘要 在半導體製程中,提昇晶圓製造良率,是降低生產成本的首要課題,也是評量晶圓製造廠優劣的重要指標之一。量產產品的良率,常常因晶圓製造過程中肇因於各種塵埃,化學溶劑,光罩缺陷,..等產生的缺陷而下降。尤其是奈米製程的良率受害更大。在微米或次微米製程技術的中,有些缺陷或許不會造成晶片失效,但當製程技術進入到奈米製程,這些非常細小的defects(或 particles),卻往往成為奈米製程晶片的頭號殺手!
在晶圓製造過程中, 以往用來提昇良率的一貫流程是利用線上缺陷檢驗系統(in-line defect inspection system)來即時偵測缺陷產生的狀況。並當晶圓製作完成,用晶圓測試機台來測試該晶圓上之晶片,以得知每個晶片的良劣及收集詳細測試資料。然後根據這些測試資料,將失效的晶片作失敗性分析(Failure Analysis)來找出造成晶片失效的缺陷,進而提供生產製造流程的改善依據。
但是,失敗性分析既耗費時日又佔用了昂貴的儀器設備資源,而且有時甚至無法真正找出缺陷。尤其當遇到緊急的良率驟降的問題,上述之流程,更無法及時有效地提供Fab 改善製程的依據。如此有可能使晶圓製造良率出現連續性的問題。須停用某一些製造機台,嚴重者甚或必須停止生產線以等待失敗性分析的結果以做為判斷或改善的依據進如此讓工廠遭遇慘重的損失。因此吾人發展一種新穎的比對系統既可降低PFA(Physical Failure Analysis)成本及加速良率改善。
本論文針對這種新穎的比對系統的發展作詳細的說明,並藉由一個晶圓代工廠的FPGA(Field Programmable Gate Array) 90奈米晶片生產線測試數據輸入這個系統來證明這個系統的可用性。首先吾人簡介缺陷密度模式與良率之關係,以解釋為何目前晶圓代工業界均採用缺陷密度以取代良率作為衡量標準。並介紹線上缺陷檢驗及晶圓測試機制。這兩個機制原本各自獨立運作以確保產品品質。我們利用既有線上缺陷檢驗系統資料庫所儲存之缺陷資料,加上與晶圓測試資料作比對。如此,將可在晶圓測試完成後立即得知造成晶片失效的缺陷及原因 ,大幅省卻失敗性分析的人力與儀器機台資源並且大幅改進良率提升的時效及新產品或技術的學習曲線!
英文摘要 As the wafer manufacturing technology scales down to nano-meter regime, the wafer process caused tiny defects occur often. In addition, the effectively killing dimension of defects is also shrunk. Thus, the in-line defect inspection executed in the wafer manufacturing for every process and layers becomes very important. On the other hand, after finish of wafer processing, there also has a wafer testing stage. Both of the inspection and test control the quality and scrapping inside a Fab independently.
Usually, after wafer testing, one starts the PFA (Physical Failure Analysis) by performing the TEM/SEM/FIB (Transmission Electron Microscope/Scanning Electron Microscope/Focused Ion Beam) in the failure chips to have a clear picture of the defects in these failure chips. The testing data provides us the valuable information to localize the defects and the layers which defects occurred. However, it also takes time and occupies the FA equipments resource, thus, impacting the manufacturing significantly. Especially, in case of solving an urgent event and/or serious yield problem, one needs the defect data and root causes immediately. Therefore, one needs a better solution with low cost and high efficiency for shortening the cycle time to improve the yield.
In this thesis, we develop a methodology for the fast yield improvement and evidence its availability with a foundry’s real production line data. Firstly, the developed methodology needs to setup and align the chip information of the GDS coordination system, the reference point or alignment marks, data format and so on. In addition, for the wafer testing raw data handling, it also requires the simple scripts to convert and translate to the topological and then physical locations. Then, compares and matches the data between the in-line defect inspection and wafer testing to find the real killer defect images without extra PFA.
論文目次 English Abstract .....................................................................................I
Chinese Abstract .................................................................................III
Contents ...............................................................................................VI
Tables Caption .....................................................................................VIII
Figures Caption ...................................................................................IX
Nomenclature ....................................................................................XV


Chapter 1 Introduction
1.1 Motivation ..................................................................................1
1.2 Preface of Thesis ........................................................................3

Chapter 2 Basic Concepts of the Methodology

2.1 In-line Defect Inspection ............................................................5
2.2 Inspection Tools ..........................................................................6
2.2.1 Viper 2430 for Automated Defect Inspection ....................6
2.2.2 eS32 for Accelerating FEOL Innovation ...........................7
2.3 Inspection Methodologies ..........................................................8
2.4 Wafer Testing .............................................................................10
2.5 Testing tools ..............................................................................11
2.5.1 T5501 Dual-head memory test system ............................12
2.6 Introduction to Testing ..............................................................12

Chapter 3 Experiment

3.1 Objective for Experiment ..........................................................15
3.2 Inspection and Test Equipment used in the experiment ............16
3.3 Procedures of Experiment .........................................................16
3.3.1 Product Selection ..............................................................17
3.3.2 In-line Defect Inspection EDA Database ..........................17
3.3.3 Setting Up Procedures ......................................................18
3.3.4 Software Set Up ................................................................20

Chapter 4 Results and Discussion

4.1 Test System Calibration and Correlation ............................23
4.2 Test procedure for the experiment ......................................24
4.3 Test Result ,Data Conversion and Matching ......................26
4.4 The Extra work for the Non-Matched chips .......................29

Chapter 5 Conclusion and Future Work

5.1 Conclusion ...........................................................................30
5.2 Prospects ..............................................................................32

References ...............................................................................................34

Acknowledgement ..............................................................................XIV

VITA .....................................................................................................XV
參考文獻 [1] Parks, H.G. “Yield modeling from SRAM failure analysis,” Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on 5-7 P. 169 – 174, March 1990
[2] Mughal, H.A., Eccleston, W., Stuart, R.A. “Spatial distribution of defects in SiO2,” Electronics Letters Volume 14, Issue 24, P. 761 – 762, November 23 1978
[3] ANSLEY, W. C : 'Computation of integrated circuit yields from the distribution of slice yields for the individual devices', IEEE Trans., ED-15, P.405 – 406,1968
[4] H.G. Parks and E.k Burke, “The Nature of Defect Size Distributions in Semiconductor Processes” International Semiconductor Manufacturing Science Symposium (ISMSS) '89 Proceedings, IEEE, Catalog Number 89CH2699-7, May 1989, Pg-131.
[5] Stapper, C.H., “On Murphy's yield integral [IC manufacture],” Semiconductor Manufacturing, IEEE Transactions on Volume 4, Issue 4, P. 294 – 297, Nov. 1991
[6] Zakzouk, A.K.M., “Factors affecting probability distribution and yield of silicon dioxide defects,” Communications, Speech and Vision, IEE Proceedings I [see also IEE Proceedings-Communications] Volume 129, Issue 3, P. 96, June 1982
[7] Berglund, C.N., “A unified yield model incorporating both defect and parametric effects,” Semiconductor Manufacturing, IEEE Transactions on Volume 9, Issue 3, P. 447 – 454, Aug. 1996
[8] Sopori, B.L.; Murphy, R.; Marshall, C., “A scanning defect-mapping system for large-area silicon substrates,” Photovoltaic Specialists Conference, 1993., Conference Record of the Twenty Third IEEE 10-14 P.190 – 194, May 1993
[9] C. H. Stapper, “Defect density distribution for LSI yield calculations,” IEEE Trans. Electron Devices, vol. ED-20, P. 655, 1973
[10] R. C. Leachman, Ed., “The competitive semiconductor manufacturing survey: Second report on results of the main phase,” University of California, Berkeley, CA, rep. CSM-08, 1994.
[11] Malaiya, Y.K.; Denton, J, “Module size distribution and defect density,” Software
Reliability Engineering, 2000. ISSRE 2000. Proceedings. 11th International Symposium on, P. 62 – 71, 8-11 Oct. 2000
[12] Stapper, C. H., “Defect Density Distribution for LSI Yield Calculations,” IEEE
Transactions on Electron Devices (Correspondence. ED-20, P. 655-657), 1973
[13] Baxter, M.L.; “Monitoring and predicting defect densities in a high volume
manufacturing facility for increasing yields,” Improving the Efficiency of IC
Manufacturing Technology, IEE Colloquium P. 6/1 - 6/3, 12 Apr 1995
[14] Chan, L.; Geuskens, B.; Mangaser, R.; Rose, K.; “BEOL yield predictions for SIA roadmap,” Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE /SEMI P. 87–90, Sept. ,10-12 1997
[15] Baxter, M.L.; “Monitoring and predicting defect densities in a high volume manufacturing facility for increasing yields,” Improving the Efficiency of IC
Manufacturing Technology, IEE Colloquium , P. 6/1 - 6/3, 12 Apr 1995
[16] Hess, C.; Weiland, L.H.; “Extraction of wafer-level defect density distributions to
improve yield prediction,” Semiconductor Manufacturing, IEEE Transactions on
Volume 12, Issue 2, P. 175–183, May 1999
[17] Rajkanan, K.; “Yield analysis methodology for low defectivity wafer fabs,” Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE
International Workshop , P. 65 – 69, 7-8 Aug. 2000
[18] Miller, R.B.; Riordan, W.C.; ” Unit level predicted yield: a method of identifying
high defect density die at wafer sort,” Test Conference, 2001. Proceedings. International , P. 1118 – 1127, 30 Oct.-1 Nov. 2001
[19] Segal, J.; Gordon, A.; Sajoto, D.; Duffy, B.; Kumar, M., “A framework for extracting defect density information for yield modeling from in-line defect inspection for real-time prediction of random defect limited yields,” Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on, P. 403 – 406, 11-13 Oct. 1999
[20] Nurani, R.K., Akella, R., Strojwas, A.J, “In-line Defect Sampling Methodology in Yield Management: An Integrated Framework” IEEE Transactions on
Semiconductor Manufacturing, Vol. 9, No. 4,November 1996
[21] Nurani, R.K., Stoller, M., Gudmundsson, D., and Shanthikumar, J.G. “Evaluating
Inspection Strategies Using Advanced Statistical Methods”. KLA-Tencor Yield
Management Solution, Vol.c 1, Issue3, P. 12 – 14, Spring 1999
[22] W. Zhang, S. H. Brongersma, T. Clarysse, V. Terzieva, E. Rosseel,W. Vandervorst, and K. Maex, “Surface and grain boundary scattering studied in beveled polycrystalline thin copper films,” J. Vac. Sci. Technol., vol. B 22, no. 4, p. 1830, 2004.
[23] K. Hinode, Y.Hanaoka, K.-I. Takeda, and S. Kondo, “Resistivity increase in ultrafine-line copper conductor for ULSIs,” Jpn. J. Appl. Phys., vol. 40, p. L1097, 2001.
[24] Hess, C.; Weiland, L.H.; “Wafer level defect density distribution using checkerboard test structures,” Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on 23-26 March 1998 P. 101 – 106


[25] T. Markas, M.Royals, and N. Kanopoulos, “On distributed fault emulation,” IEEE Computer, vol. 23, pp. 40-52, Jan. 1990
[26] K.-T Cheng, S.-Y. Huang, and W.-J. Dai, “Fault emulation: A new approach to fault grading,” in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD, pp. 681-686), 1995
[27] J.-H. Hong, S.-A. Hwang, and C.-W. Wu, “An FPGA-based hardware emulator for fast fault emulation, ”in Proc. Midwest Symp. Circuits Syst.,Ames, IA, Aug.1996
[28] Xilinx, The Programmable Gate Array Data Book, Xilinx, Inc., San Jose, CA, 1996

------------------------------------------------------------------------ 第 5 筆 ---------------------------------------------------------------------
系統識別號 U0026-1007201221402000
論文名稱(中文) 桿件元素動力分析之破壞研究
論文名稱(英文) Dynamic Failure Analysis of Bar Elements
校院名稱 成功大學
系所名稱(中) 土木工程學系碩博士班
系所名稱(英) Department of Civil Engineering
學年度 100
學期 2
出版年 101
研究生(中文) 陳柏勳
學號 N66991106
學位類別 碩士
語文別 中文
口試日期 2012-06-27
論文頁數 96頁
口試委員 指導教授-徐德修
口試委員-朱聖浩
口試委員-朱世禹
口試委員-侯建元
關鍵字(中) 鋼架結構
ANSYS
有限元素法
桿件元素
動力
破壞分析
關鍵字(英) steel frame
ANSYS
finite element method
bar element
dynamic load
failure analysis
學科別分類
中文摘要 由於電腦輔助分析軟體的發展趨於成熟,使有限元素分析技術愈來愈受歡迎且逐漸必須被土木營造業所普遍採用,可使建築結構達到更精緻的的設計,確保結構物的安全水準。鋼架為公共設施中常見之結構體,在成本與安全的雙重考量下,鋼架內部的斜撐桿件可有多種不同設計,本文針對不同斜撐桿件進行分析比較之工作。
研究中利用電腦輔助分析軟體ANSYS Workbench來分析鋼架搭配上不同的斜撐桿件設計,軟體中可進行材料彈塑性特性的設定,進行非線性動力行為分析。研究中除參考公共設施的鋼架設計資料,並輔以ANSYS Workbench DesignModeler繪製鋼架及斜撐桿件模型,利用所測試出的破壞靜力,將此破壞靜力轉換成動力去進行桿件的破壞分析,並進行變位分析及測試應力應變是否符合所假設的材料特性;最後,針對鋼架結構施於El Centro地震加速度,探討其破壞模式及變位量情形並進行不同設計之優劣比較。

關鍵字:鋼架結構、ANSYS、有限元素法、桿件元素、動力、
破壞分析
英文摘要 Due to the highly development of the computer-aided analytic software, finite element method has been much more popular and commonly used in civil engineering industry. In addition to enhance the design and strength of the buildings, it helps to improve the safety of the buildings, including steel structures. Safety and economy no doubt are the main concerns to engineers in the structural design process.
For the purpose to investigate the behavior of the structural responses in detail, software package ANSYS is used herein for the simulation analysis. It not only have the interface to set the material properties, but also to set the yield stress and failure stress. Mainly, three parts of work have done: firstly, the structural model is set by ANSYS Workbench DesignModeler through the data collected. Secondly, the tested static failure load is reffered into dynamic load to find the consistency of the stress-strain relations with the pre-set material properties. Finally, the failure mode and the responses of the frame members are investigated in detail when the structure is subjected to El Centro earthquake, and concluded with comparisons.

Keywords: steel frame, ANSYS, finite element method, bar element,
dynamic load, failure analysis
論文目次 摘要.........................................................Ⅰ
致謝.........................................................Ⅲ
目錄.........................................................Ⅴ
表目錄.......................................................Ⅶ
圖目錄.......................................................Ⅷ
第一章 緒論 1
1-1 前言 1
1-2 研究動機與目的 1
1-3 研究方法 3
1-4 文獻回顧 5
1-5 章節提要 9
第二章 理論基礎 10
2-1有限元素法 10
2-2 ANSYS有限元素分析軟體 11
2-2.1 元素種類 12
2-2.2 結構分析 15
2-3 鋼斜撐的基本理論與強度分析 16
2-3.1 鋼材料應力-應變關係 16
2-3.2 降伏條件準則 18
2-4 拉力與壓力之破壞理論分析 19
2-4.1 拉力理論分析 20
2-4.2 壓力理論分析 20
2-4.3 彈性挫屈理論與非彈性挫屈理論 20
2-5 動力分析之理論 23
第三章 鋼架及斜撐桿件模型之規劃與模擬 29
3-1 鋼架及斜撐桿件基本材料特性 29
3-2 實體模型的建立 31
3-2.1 鋼架之設計尺寸及結構型式 31
3-2.2 斜撐桿件模型的建立 33
3-3 元素網格的劃分 36
3-3.1 使用之元素型式 36
3-3.2 網格分割 38
3-4 接觸元素的設定 42
3-5 邊界條件與載重的設定 43
3-6 結果顯示的設定 47
第四章 數值模擬分析結果 48
4-1 數值模擬之目標 48
4-2 數值模擬分析結果 48
4-2.1基準地震力分析 49
4-2.2 初始降伏點分析 56
4-2.3 結構破壞力分析 72
第五章 結論與建議 91
5-1 結論 91
5-2 未來展望 93
參考文獻 94
參考文獻 1. Bathe, K. J., “Finite Element Procedures”, Prentice-Hall, Inc., New Jersey, 1996.

2. Becker, E. B., Carey, G. F., and Oden, J. T., “Finite Element: An Lnteroduction Volume I”, Prentice-Hall, Inc., New Jersey, 1981.

3. Bennett J. A., and Botkin M. E., “Structural Optimization Approach with Geometric Description and Adaptive Mesh Refinement”, AIAA Journal, Vol. 23, pp. 458, 1985.

4. Cheu T. C., “Procedures for Shape Optimization of Gas Turbine Disks”, Computers and Structures, Vol. 34, pp. 1, 1990.

5. Groth H. L. , and Nordlund P. , “Shape Optimization of Bonded Joints” , Int. J. Adhesion and Adhesives, Vol. 11, pp. 204, 1991.

6. Huei-Huang Lee, “Finite Element Simulations With ANSYS Workbench 12 Theory-Applications-Case Studies”, Schroff Development Corporation, 2010.

7. Huei-Huang Lee, “Finite Element Simulations With ANSYS Workbench 13 Theory-Applications-Case Studies”, Schroff Development Corporation, 2011.

8. I. Elishakoff, J. Arbocz, C. D. Babcock,jr. and A. Libai., “Buckling of Structures─Theory and Experiment” , Elsevier Science Publishers B.V. , 1988.

9. Kamiya N. and Kita E. , “Boundary Element Method for Quasi-harmonic Differential Equation with Application to Stress Analysis and Shape Optimization of Helical Spring” , Computers and Structures, Vol. 37, pp. 81, 1990.

10. Mahmood M. S. and Davood R. , “Analysis and optimization of a composite leaf spring” , Composite Structures,Vol. 60, pp. 317, 2003.

11. Mourad, Sherif Ahmed, Ph.D.“Modal Analysis And Buckling Effects On Steel Structures Under Dynamic Loading” , Ph. D. Dissentation, University of California, Irvine, 1990.

12. Rao, S. S. , 陳昭昌編譯,有限元素法-工程上之應用“The Finite Element Method in Engineering”,復文書局,1989.

13. Turner, M. J. , Clough, R. W. , Martin, H. C. and Topp, L. J. , “Stifness and Deflection Analysis of Complex Structures” , Journal of Aeronautical Sciences, 1956.

14. Zahavi E. , “The Finite Element Method in Machine Design” , Prentice-Hall, 1992.

15. Zahavi, E. and Barlam, E. , “Nonlinear Problems in Machine Design” , CRC Press LLC, 2000.

16. Zhu, B. , Rao, B. , Jia, J. and Li, Y. , ”Shape Optimization of Arch Dam for Static and Dynamic Loads” , J. Structural Engineering, 1992.

17. 夸克工作室,有限元素分析 ANSYS 與 Mathematica. 基礎篇,知城數位科技股份有限公司,2001.08.

18. 林政源,小波有限元素法再結構振動之應用,國立成功大學機械工程學系碩士論文,2002.06.

19. 林煒凱,有限元素ANSYS分析橢圓形凹槽薄壁管在循環彎曲負載下之力學行為,國立成功大學工程科學研究所碩士論文,2008.06.

20. 林敬銘,架空移動式起重機結構強度分析及桁架最佳化設計,國立成功大學機械工程學系碩士論文,2010.06.

21. 高崇洋、王書龍及康淵,有限元素法在塔式起重機結構強度之分析,行政院勞工委員會勞工安全衛生研究所季刊,第6卷第4期,1998.12.

22. 張智奇,鋼管支撐材料疲勞性能研究,行政院勞工委員會勞工安全衛生研究所,2005.02.

23. 許豐榮,結構補強用斜撐之彈塑性行為數值模擬,國立中央大學土木工程學系碩士論文,2005.01.

24. 楊詠超,引擎排氣歧管固定鉗之電腦輔助疲勞分析,逢甲大學航太與系統工程學系碩士論文,2007.07.

25. 趙守忠,有限元素分析的前後處理程式發展,國立台灣工業技術學院工程技術研究所營建工程技術學程碩士論文,1992.06.

26. 劉晉奇、褚晴暉,有限元素分析與ANSYS的工程應用,滄海書局,2006.

27. 蔡國忠,ANSYS Workbench有限元素分析及工程應用,加樺國際有限公司,2008.07.

28. 蔡國忠,ANSYS Workbench有限元素分析及工程應用,易習圖書,2011.04.

29. 蘇志彥,造型椅有限元素分析與設計,國立成功大學工程科學研究所碩士論文,2007.06.

30. 羅際揚,ANSYS應用在桿件元素之破壞分析,國立成功大學土木工程學系碩士論文,2011.06.

------------------------------------------------------------------------ 第 6 筆 ---------------------------------------------------------------------
系統識別號 U0026-1907201218440900
論文名稱(中文) ANSYS應用於3D桿件元素之結構分析
論文名稱(英文) Analysis of 3D Member Structures by Software ANSYS WORKBENCH
校院名稱 成功大學
系所名稱(中) 土木工程學系碩博士班
系所名稱(英) Department of Civil Engineering
學年度 100
學期 2
出版年 101
研究生(中文) 張群郁
學號 N66991067
學位類別 碩士
語文別 中文
口試日期 2012-06-27
論文頁數 131頁
口試委員 指導教授-徐德修
口試委員-朱世禹
口試委員-朱聖浩
口試委員-侯建元
關鍵字(中) 鋼結構
ANSYS
有限元素法
斜撐桿件
塑性
非線性
破壞分析
關鍵字(英) Steel structure
ANSYS
finite element method
solid element
plastic
nonlinearly
failure analysis
學科別分類
中文摘要 近年來,隨著建築技術的精進,結構物的強度與安全性也隨之提升,鋼結構設計亦不斷改進,並廣泛應用於公共工程當中,近年發展之輕型三維類桁架,鋼架結構多有應用在結構體中,此結構每單位重量的強度及勁度相當高。
材料在彈性階段時之結構行為已被前人所熟悉,當達到降伏進入塑性階段後,結構行為無法單純以理論推導而得,其中且因反覆的由彈性進入塑性、塑性進入彈性而更顯複雜。
類桁架結構與傳統桁架結構行為不同,傳統桁架載重僅作用於節點處,但類桁架載重可作用於桿件上,擁有桁架的幾何形狀,卻有鋼架的結構行為,桁架與類桁架兩者結構行為完全不相同。為了熟知三維類桁架結構在彈塑性間之行為,本研究利用電腦輔助工程分析軟體ANSYS Workbench來分析結構體材料達降伏進入塑性階段後之行為,如應力、變位、極限載重、破壞模式等進行研究探討,藉此獲得其彈塑性動力行為反應,並可據以進行合理之結構設計。
英文摘要 In recent years, building design and construction technology have been developed to enhance the strength and safety of the structures, including steel structures which are widely used in public works. Three dimensional truss-like steel frame which behaves with very high strength and stiffness is widely used.
Although it is already clear knowledge as structures vibrate in elastic stage, it will become much more complicated when it vibrate beyond elastic limit and the material goes into yielding stage. The structures behaves nonlinearly.
In order to investigate the dynamic behavior of the three dimensional truss-like steel frame, computer-aided engineering analysis software package ANSYS Workbench is used here in. Dynamic behaviors of the mentioned structure, such as stress, deflections, ultimate loads, and failure modes…etc. are detected in detail. It is expected to help engineers to face the design work in the future.
論文目次 摘要 Ⅰ
誌謝 Ⅲ
目錄 VI
表目錄 IX
圖目錄 X
第一章 緒論 1
1-1 研究動機與目的 1
1-2 研究方法 4
1-3 文獻回顧 5
1-4 章節提要 10
第二章 研究理論基礎 11
2-1有限元素法(Finite Element Method)11
2-2 ANSYS WORKBENCH有限元素分析軟體 13
2-2.1 ANSYS WORKBENCH有限元素分析軟體 13
2-2.2 ANSYS WORKBENCH分析流程 16
2-2.3 元素種類 22
2-3基本理論與強度分析 27
2-3.1 鋼材拉伸試驗之應力-應變關係 28
2-3.2 降伏(破壞)準則 33
2-4 桿件之拉力與壓力破壞理論分析 36
2-4.1 桿件之拉力理論分析 36
2-4.2 桿件之壓力理論分析 37
2-4.3 彈性挫屈理論 37
2-4.4非彈性挫屈理論 42
2-5動力分析理論 44
2-5.1 Newmark Method 50
2-5.2 HHT(Hilber Hughes Taylor Method) 53
2-5.3 Newton Raphson Method 56
第三章 三維桿件模型之設計 59
3-1桿件之基本材料特性 59
3-2 實體模型的建立 61
3-2.1設計尺寸及結構型式 61
3-3 元素網格的劃分 67
3-3.1 使用之元素型式 67
3-3.2 建立網格設定 68
3-4 邊界條件與載重設定 71
第四章 數值模擬分析結果 75
4-1 數值模擬之目標 75
4-2 數值模擬之載重設定 76
4-3 數值模擬分析結果 79
4-3.1靜力初始降伏點分析 79
4-3.2 靜力結構破壞分析 83
4-3.3 靜力卸載後殘餘應力分析 95
4-3.4動力初始降伏點分析 102
4-3.5 動力結構破壞分析 110
第五章 結論與未來展望 122
5-1 結論 123
5-2 未來展望 126
參考文獻 127
附錄 130


參考文獻 1. ANSYS, Inc., ANSYS Help System, version. 12. 0. 1, 2009.
2. Bathe, K. J., “Finite Element Procedures”, Prentice-Hall, Inc., New Jersey, 1996.
3. Becker, E. B., Carey, G. F., and Oden, J. T., “Finite Element: An Lnteroduction Volume I”, Prentice-Hall, Inc., New Jersey, 1981.
4. Bennett J. A., and Botkin M. E., “Structural Optimization Approach with Geometric Description and Adaptive Mesh Refinement”, AIAA Journal, Vol. 23, pp. 458, 1985.
5. Huei-Huang Lee, “Finite Element Simulations With ANSYS Workbench 12 Theory-Applications-Case Studies”, Schroff Development Corporation, 2010.
6. H. M. Hilber, T. J. R. Hughes, and R. L. Taylor. “Improved Numerical Dissipation for Time Integration Algorithm in Structural Dynamics”. Earthquake Engineering and Structural Dynamics. Vol. 5. pp. 283. 1977.
7. J.N. Reddy, “An Introduction to the Finite Element Method. Third edition”. McGraw-Hill, 2006.
8. Mahmood M. S., and Davood R., “Analysis and optimization of a composite leaf spring”, Composite Structures, Vol. 60, pp. 317, 2003.
9. M.R. Maheri, Sahebi A. Use of Steel Bracing in Reinforced Concrete Frames. Engineer Structures. 19(12):1018–24., 1997.
10. O.C. Zienkiewicz. “The Finite Element Method”, McGraw-Hill Company, London, 1977.
11. Richard L. B., J. D. Faires, “Numerical Analysis”, 8th Edition, Thomson Brooks/Cole, 2005.
12. R. Courant, K. O. Friedrichs, H. Lewy. Uber die Partiellen Differenzengleichungen der Mathematischen Physik. Math Annalen, 100, 1928.
13. R.W Clough, The finite element method in plane stress analysis. Proceedings of American Society of Civil Engineers, 2nd Conference on Electronic Computation, Pittsburgh, PA, pp. 345-378, Sep. 1960.
14. Rao, S. S., 陳昭昌編譯,有限元素法-工程上之應用“The Finite Element Method in Engineering”, 復文書局,1989.
15. Turner, M. J., Clough, R. W., Martin, H. C., and Topp, L. J.,“Stifness and Deflection Analysis of Complex Structures”, Journal of Aeronautical Sciences, Vol. 23, 1956.
16.毛昭綱,材料力學,全華圖書,2008.05.
17.李輝煌,ANSYS工程分析基礎與觀念,高立圖書,2005.05.
18.李文海,非彈性階段P-∆之效應對高層鋼架耐震能力之影響,第七屆結構工程研討會,大溪,2004.08.
19.林永盛,基礎結構動力,文笙書局,1991.11.
20.林俊宏,有限元素ANSYS分析圓管在循環彎曲負載下之力學行為,國立成功大學工程科學研究所碩士論文,2006.06
21.林煒凱,有限元素ANSYS分析橢圓形凹槽薄壁管在循環彎曲負載下之力學行為,國立成功大學工程科學研究所碩士論文,2008.06
22.許豐榮,結構補強用斜撐之彈塑性行為數值模擬,國立中央大學土木工程學系碩士論文,2005.01.
23.馮 康,基於變分原理的差分格式,應用數學與計算數學,1965.
24.彭淑娟,三維類桁架結構材料之力學性質分析,國立成功大學土木工程學系碩士論文,2004.06.
25.楊詠超,引擎排氣歧管固定鉗之電腦輔助疲勞分析,逢甲大學航太與系統工程學系碩士論文,2007.07.
26.何長慶,鋼結構的材料,鋼結構會刊第十六期,2003.08.
27.黃慶淵、張耀南、王璽貴、楊正生,橋梁用鋼的性質要求與發展現況,鋼結構會刊第三十一期,2008.07.
28.賴政忠,鋼筋混凝土梁柱構件於火害中強度評估之研究,國立成功大學土木工程學系碩士論文,2006.06.
29.羅際揚,ANSYS應用在桿元素之破壞分析,國立成功大學土木工程學系碩士論文,20011.06.
30.蘇志彥,造型椅有限元素分析與設計,國立成功大學工程科學研究所碩士論文,2007.06.
31.蘇慶泯,韌性斜撐構材之遲滯行為與斷裂預測,國立台灣科技大學,2000

------------------------------------------------------------------------ 第 7 筆 ---------------------------------------------------------------------
系統識別號 U0026-2107201116490900
論文名稱(中文) 運用多重碎形理論於滾珠螺桿系統之訊號分析
論文名稱(英文) Applocation of Multifractal Theory to the Signal Analysis of Ball-Screw System
校院名稱 成功大學
系所名稱(中) 機械工程學系碩博士班
系所名稱(英) Department of Mechanical Engineering
學年度 99
學期 2
出版年 100
研究生(中文) 張閔期
學號 n16981151
學位類別 碩士
語文別 中文
口試日期 2011-07-12
論文頁數 105頁
口試委員 指導教授-林仁輝
口試委員-邱源成
口試委員-劉正倫
口試委員-屈岳陵
關鍵字(中) 多重碎形理論
滾珠螺桿
訊號分析
關鍵字(英) multifractal theory
ball-screw
failure analysis
學科別分類
中文摘要 本研究利用多重碎形理論作為訊號分析方法,用以解析高速滾珠螺桿機台運轉之訊號以達到失效分析之目的。利用單一碎形理論中的維度D_s值及高度尺度參數G值能反應出機台運轉時之狀態,但僅藉由此二碎形參數之趨勢變化所能得知的訊息仍屬有限。本文之特點為加入可描述碎形維度在空間或時間中分佈現象的多重碎形理論,以不同之尺度指數區分強弱訊號並顯示碎形維度分佈情形,許多現象便在此分類後再分析的過程顯示。本文之另一特點為運用多重碎形之概念進一步分析高度尺度參數,高度尺度參數原為運用於描述物體表面形貌之起伏,而後亦被運用在訊號分析中,多重碎形理論中並無高度尺度參數或類似之參數,本文嘗試以瞬時高度尺度參數分佈偏度係數作為分析方法,並得到其與能反映出潤滑油脂之溢漏狀況之結果。本文並針對高速滾珠螺桿機台之訊號特性加以分析,說明特定訊號如量測雜訊、球通訊號反應在多重碎形分析之特徵值。本研究之研究方法以建立軟體提供業界使用。
經多重碎形理論分析後,訊號在試件發生擦損前後顯示出明顯的差異,發生擦損後之訊號多重碎形頻譜曲線開口遠寬於發生擦損之前,反應出接觸行為較為不穩定,這是利用單一碎形理論分析時所無法觀察的。針對扭矩及振動訊號之多重碎形分析,在滾珠螺桿之軸承失效故障前確實能反映出異狀,在故障發生前三小時其多重碎形頻譜曲線開口亦越來越寬,反應其訊號越來越不穩定。多重碎形理論有潛力運用於複雜機構之機台之失效分析、預測,機械元件在失效前很可能產生些微的徵兆,並影響各種等訊號,多重碎形理論提供一個跨越尺度的角度來篩選、解析這些徵兆。
英文摘要 In this thesis, we use multifractal theory as a signal processing method to resolve the ball-screw signal to achieve failure analysis. Monofractal and topothesy can reflect the state of running machines, but there is only a few information we could get from those two values. One of the unique of this study is using multifractal theory which characterized the uneven distribution of monofractal in time or space, signal is discriminated by different Hölder exponent and then analyze fractal dimension respectively, some phenomenon was shown during those processes. Another feature of this study is to combine multifractal theory with topothesy. The original function of topothesy is characterizing the undulating of surface topography, then topothesy is used in signal process to represent the amplitude. But there is no topothesy or other similar parameters in multifractal theory, in this study, we analyze the distribution of instantaneous topothesy as a method to failure analysis.
The result of experiments shows huge difference between scuffing and non-scuffing after analyzed by multifractal theory, which can not show in monofractal analysis; multifractal analysis of vibration and torque signal can reflect the condition of ball-bearing failure, those cases show that it is potentially to use multifractal theory to failure analysis. We also describe the character of ball-screw signal, identify how the specific signal such as ball-pass signal and noise show in multifractal spectra.
論文目次 摘要 I
ABSTRACT III
致謝 IV
目錄 V
表目錄 VIII
圖目錄 IX
第一章 緒論 1
1-1前言 1
1-2文獻回顧 2
1-3研究動機與目的 5
1-4本文架構 6
第二章 基本理論 8
2-1數位訊號處理 8
2-1-1取樣定理 8
2-1-2誤差與失真 9
2-2碎形理論與碎形參數之量測 10
2-2-1碎形理論簡介 10
2-2-2自相似性與自仿射性 11
2-2-3碎形參數之計算方法 13
2-2-4碎形區間之選取 16
2-3多重碎形理論 17
2-3-1廣義碎形維度 18
2-3-2多重碎形頻譜 20
2-3-3 多重碎形參數之轉換與求法 21
2-4 偏度係數 23
第三章 實驗步驟與方法 35
3-1 實驗機構與分析 35
3-1-1 實驗機構介紹 35
3-1-2球通頻率之計算與量測 37
3-2實驗儀器與規畫 38
3-2-1 實驗儀器介紹 38
3-2-2參數設定 38
3-3實驗步驟 39
3-3-1 前置作業 39
3-3-2 實驗步驟 40
3-4 訊號擷取及處理流程 40
第四章 結果與討論 49
4-1滾珠螺桿訊號之單一碎形理論分析 49
4-1-1操作參數與再現性討論 50
4-1-2不同粗糙度螺帽之碎形參數 51
4-1-3耐久性試驗 53
4-2從單一碎形到多重碎形 54
4-2-1瞬時碎形參數分析 54
4-2-2 瞬時碎形參數與多重碎形 56
4-3滾珠螺桿訊號之多重碎形分析 60
4-3-1 滾珠螺桿基本訊號分析 60
4-3-2 潤滑油脂狀態監測 62
4-3-3 軸承失效分析 64
第五章 結論與建議 97
5-1 結論 97
5-2 建議與未來展望 98
參考文獻 100

參考文獻 [1] E. N. Lorenz, 1963, “Deterministic Nonperiodic Flow” Journal of the Atmospheric Sciences, vol.20, pp.130-141.
[2] B. B. Mandelbort, 1982, "The Fractal Geometry of Nature," W. H. Freeman, New York.
[3] 葛世榮、朱華,2005,"摩擦學的分形",機械工業出版社,中國。
[4] G. Zhou, M. Leu and D. Blackmore, 1995, "Fractal Geometry Modeling with Applications in Surface Characterisation and Wear Prediction," International Journal of Machine Tools and Manufacture, vol.35, No.2, pp.203-209.
[5] H. Zhou, S. Ge, X. Cao and W. Tang, 2007 “The Changes of Fractal Dimensions of Frictional Signals in the Running-In Wear Process”, Wear, vol.263, pp.1502–1507.
[6] B. B. Mandelbrot, 1989, “Multifractal Measures, Especially for the Geophysicist”, Pure and Applied Geophysics, vol. 131, pp.5-42
[7] U, Frisch and G, Parisi, 1985, “On the Singularity Structure of Fully Developed Turbulence.” Turbulence and Predictability in Geophysical Fluid Dynamics, Amsterdam, North-Holland.
[8] A. R. Rojas A. M. Diosdado, C. G. P. Miller, and F. A. Brown, 2004, “Spectral and Multifractal Study of Electroseismic Time Series Associated to the Mw=6.5 Earthquake of 24 October 1993 in Mexico” Natural Hazards and Earth System Sciences, vol.4, pp. 703–709.
[9] C. Godano and V. Caruso, 1995, “Multifractal Analysis of Earthquake Catalogues”, Geophysical Journal International , vol.121, pp.385-392.
[10] P.C. Ivanov, N. Amaral, A.L. Golberger, S. Havlin, M.G. Rosenblum, Z.R. Struzik, and H.E. Stanley, 1999 “Multifractality in Human Heartbeat Dynamics”, Nacture,vol.399, pp.461-465.
[11] G. Schmitt and L. Seuront, 2001, “Multifractal Random Walk in Copepod Behavior”, Physica A, vol.301, pp.375–396.
[12] S. J. Loutridis, 2008, “Self-Similarity in Vibration Time Series: Application to Gear Fault Diagnostics” Journal of Vibration and Acoustics, vol. 130, pp.0310041-0310049.
[13] M. H. Benbouzid, 2000, “A Review of Induction Motors Signature Analysis as a Medium for Faults Detection”, IEEE Transactions On Industrial Electronics, vol. 47, No. 5, pp.984-993.
[14] H. Yang , J. Mathew and L. Ma, 2005, “Fault Diagnosis of Rolling Element Bearings Using Basis Pursuit”, Mechanical Systems and Signal Processing, vol.19, pp.341-356.
[15] H. M, Monavar, H. Ahmadi and S.S. Mohtasebi, 2008, “Prediction of Defects in Roller Bearings Using Vibration Signal Analysis”, World Applied Sciences Journal, vol.4, No.1, pp.150-154.
[16] V. K. Rai and A. R. Mohanty, 2007, “Bearing Fault Diagnosis Using FFT of Intrinsic Mode Functions in Hilbert–Huang Transform”, Mechanical Systems and Signal Processing, vol. 21, pp.2607-2615.
[17] M. Costa, A. L. Goldberger and C. K. Peng, 2002, “Multiscale Entropy Analysis of Complex Physiologic Time Series”, Physical Review Letters, vol.89, No. 6, pp.0681021-0681021.
[18] J. L. Chang, J. A. Chao, Y. C. Huang and J. S. Chen, 2010, “Prognostic Experiment for Ball Screw Preload Loss of Machine Tool through the Hilbert-Huang Transform and Multiscale Entropy Method” Proceedings of the 2010 IEEE International, pp.376-380.
[19] B. S. Raghavendra, Student Member, IEEE, and D. N. Dutt, 2008, “Signal Characterization Using Fractal Dimension”, TENCON 2008 - 2008 IEEE Region 10 Conference, pp.1-4.
[20] Y. Tokunaga, T. Igarashi and and T. Sugiura, 1989, “Studies on the Sound and Vibration of Ball Screw” Transactions of the Japan Society of Mechanical Engineers, Part C, vol.55, No.520, pp.2945-2950.
[21] 蘇栢賢,2005,“滾珠導螺桿振動噪音之研究” ,國立清華大學碩士論文
[22] 王建文,2006, “滾珠螺桿低頻噪音源之鑑別即改善研究”, 國立清華大學碩士論文
[23] J. P. Hung, S. S. Wu, and Y. Chiu, 2004, “Impact Failure Analysis of Re-circulating Mechanism in Ball Screw” Engineering Failure Analysis, vol.11, pp.561-573.
[24] S. Frey and M. Walther, 2010, “Periodic Variation of Preloading in Ball Screws” Production Engineering Research and Development, vol. 4, pp.261-267.
[25] M. Pharr and G. Humphreys, 2004, “Physically Based Rendering: From Theory to Implementation”, Morgan Kaufmann, USA
[26] H. Nyquist, 1928, "Certain Topics in Telegraph Transmission Theory," Trans. AIEE, vol.47, pp.617-644.
[27] C. Y. Wonga, Y. N. Kwonb and S. Criddlec, 2009, “Use of Atomic Force Microscopy and Fractal Geometry to Characterize the Roughness of Nano-, Micro-, and Ultrafiltration Membranes”, Journal of Membrane Science, vol.340, pp.117–132.
[28] B. Dubuc, J. F. Quiniou, C. R.Carmes, C. Tricot and S. W. Zucker, 1989, "Evaluating the Fractal Dimension of Profiles", Physical Review A, vol.39, pp.1500-1512.
[29] J. Nogues, J. L. Costa and K.V. Rao, 1992, "Fractal Dimension of Thin Film Surfaces of Gold Sputter Deposited on Mica: a Scanning Tunneling Microscopic Study ", Physica A, vol.182, pp.532-541.
[30] 孫毅興,2010,"利用碎形理論建立量測訊號即時監測技術與磨潤行為關聯性之研究",國立成功大學碩士論文
[31] M.V. Berry, and D. H. Berman, 1980, "On the Weierstrass - Mandelbort Fractal Function", Proceedings of Royal Society of London, A370, pp.459-484.
[32] W. Yan, and K. Komvopoulos, 1998, "Contact Analysis of Elastic Plasitc Fractal Surface," Journal of Applied Physics, vol.84, pp.3617-3624.
[33] T.C. Halsey, M.H. Jensen, L.P. Kadanoff, I. Procaccia and B.I. Shraiman ,1986, “Fractal measure and their singularities: The characterization of strange sets”, Physcial Review A, vol.33, pp.1141–1151 .
[34] S. Laurent, 2010, “Fractals and Multifractals in Ecology And Aquatic Science”, CRC Press/Taylor & Francis, USA
[35] A. Rneyi,1970 ,”Probability Theory”, North-Holland, Amsterdam
[36] P. Grassberger, 1983, “Generalized Dimensions of Strange Attractors”, Physicas Letters A, vol.97, pp.227-230.
[37] H. Hentschel and I. Procaccia, 1983,” The Infinite Number of Generalized Dimensions of Fractals and Strange Attractors”, Physica D: Nonlinear Phenomena, vol.8, pp. 435-444.
[38] T. Vicsek, 1993, “Fractal Growth Phenomena”, Word Scientific, Singapore
[39] H. Takayasu, 1997, “Fractals in the Physical Sciences”, Manchester University Press, Manchester.
[40] 蘇致遠,2004,"音樂及DNA序列之多重碎形分析",國立台灣大學博士論文
[41] C.J.G. Evertsz and B.B. Mandelbrot, 1992, “ Multifractal Measures, Chaos and Fractals: New Frontier of Science”, Springer, USA
[42] A. Belussi, C. Faloutsos, 1995, “Estimating the Selectivity of Spatial Queries Using the Correlation Fractal Dimension”, in 21th International Journal on Very Large Data Bases, pp.1-26
[43] 魏進忠,2003,"單螺帽雙圈滾珠螺桿在預負荷及潤滑作用條件下運動機制與機械性能的理論分析及實驗印證",國立成功大學博士論文
[44] 洪政豪、林仁輝、李旺龍、張育斌、朱孝業、魏進忠,2011, "高速高精度滾珠螺桿之性能提升研究",國家科學委員會輔助產學合作計畫結案報告。
[45] 劉志宏,2011,"高速滾珠螺桿振動響應與扭矩分析",國立虎尾科技大學碩士論文
[46] 葉承翔,2011,"高速滾珠螺桿熱效應對定位性能研究",國立虎尾科技大學碩士論文
[47] 康庭嘉,2011,"滾珠螺桿之螺帽熱變位分析研究",國立高雄應用科技大學碩士論文
[48] J.K. Kantelhardt, S.A. Zschiegner, E. Koscielny-Bunde, S. Havlin, A. Bunde, H.E. Stanley, 2002, "Multifractal detrended fluctuation analysis of nonstationary time series", Physica A, vol.316, pp.87-114.

------------------------------------------------------------------------ 第 8 筆 ---------------------------------------------------------------------
系統識別號 U0026-2508201115275300
論文名稱(中文) 壓電蠕動式微幫浦的錯誤分析之研究
論文名稱(英文) Failure Analysis for Peristaltic Micropumps with PZT Actuators
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 2
出版年 100
研究生(中文) 陳柄良
學號 n26980149
學位類別 碩士
語文別 英文
口試日期 2011-07-01
論文頁數 31頁
口試委員 指導教授-張凌昇
口試委員-陳明坤
口試委員-許藝菊
關鍵字(中) 微機電系統
微型幫浦
鋯鈦酸鉛驅動器
錯誤分析
BVD模組
壓電電性模組
電性分析
關鍵字(英) microelectromechanical systems (MEMS)
Micropump
Lead zirconate titanate (PZT)
failure analysis (FA)
BVD (Butterworth-Van Dyke)
electrical analysis
學科別分類
中文摘要 目前微型幫浦已廣泛應用在生醫研究上。其中以壓電材料(PZT)為致動器的微型幫浦最適合發展高精準度控制的藥物輸送系統。在微幫浦製造過程中容易出現一些不良因素而使得微型幫浦在組裝上或操作上出現故障情形,而使得微型幫浦的效能降低。而在大量的微型幫浦中去找出有瑕疵的微型幫浦是很困難且耗時的,所以本研究提供一個方便且快速的方法來做檢測。在致動器組裝成微型幫浦前,透過電性分析的量測方式做快速檢測,將有問題的致動器排除掉,減少製作出有瑕疵的微型幫浦之機率。藉著錯誤分析這種方法我們不只可以很快地判斷出有瑕疵的微型幫浦而且還可以判斷故障的類型。
英文摘要 The research and development of microelectromechanical systems (MEMS) have been growth dramatically in the last 20 years. Interest in Micropump miniaturization has led to the development of bulk lead zirconate titanate (PZT) for actuators and MEMS. The PZT actuators are most likely to be applied in implementations for a portable micropump for medical drug delivery. A typical micropump is a MEMS device, which provides the actuation source to transfer the fluid from the drug reservoir to the body with precision, accuracy and reliability. Failure detection is a key ingredient in successful micropump process development, attainment of high production yields and assurance of long-term reliability. In this paper, we present the electrical analysis by using the modified Butterworth-Van Dyke (BVD) model for valveless peristaltic PZT micropump fabricating analysis. By observing the elements value of the characteristics such as Rx and C0 can detect the faults and classify the failure type easily. The failure analysis (FA) of micropump assembling process is focus on the common failures: (a) PZT cracked (b) Unevenly silver epoxy (c) PZT inversion. The analysis approach combining experiment with the circuit model is helpful to understand and PZT micropump fabricating reliability. It can help to detect the defect of the peristaltic PZT micropump and classify the failure type.
論文目次 中文摘要 I
Abstract II
Acknowledgment IV
Content V
List of Tables VII
List of Figures VIII
Chapter 1 Introduction 1
1.1 Motivation and background 1
1.2 Organization of the dissertation 4
Chapter 2 Modified BVD model 5
2.1 Piezoelectric micropump 5
2.2 Experiment set-up 7
2.3 Electrical evaluation method 9
Chapter 3 Experiment Result and Discussion 12
3.1 Cracked PZT 14
3.2 Unevenly silver epoxy 19
3.3 PZT inversion 22
Chapter 4 Conclusions 27
Reference 29
參考文獻 [1] Nisar, A, Afzulpurkar, N, Mahaisavariya, B, Tuantranont, A. MEMS-based micropumps in drug delivery and biomedical applications. In: Sensors and Actuators B: Chemical 130; p. 917–42. 2008.
[2] Fair RB, Khlystov A, Srinivasan V, Pamula VK, Weaver KN. Integrated chemical/biochemical sample collection, pre-concentration, and analysis on a digital microfluidic lab-on-a-chip platform. In: Proc SPIE 5591; p. 113-24. 2004.
[3] Andersson H, Van den Berg A. Microfluidic devices for cellomics: A review. In: Sensors and Actuators B: Chemical 92; p. 315-25. 2003.
[4] Merlijn van Spengen W, Pusers R, Mertens R, Ingrid De Wolf. Characterization and failure analysis of MEMS: high resolution optical investigation of small out-of-plane movements and fast vibrations. In: Microsystem Technologies 10; p. 89-96. 2004.
[5] Lintel van HTG, Pol van de FCM, Bouwstra S. A piezoelectric micropump based on micromachining of silicon. In: Sensors and Actuators 15; p. 153-67. 1988.
[6] Jang LS, Li YJ, SJ Lin, Hsu YC, Yao WS, Tsai MC, Hou CC. A stand-alone peristaltic micropump based on piezoelectric actuation. In: Biomed Microdevices 9; p. 185-94. 2007.
[7] Rapp R, Schomburg WK, Maas D, Schulz J, W. Stark. LIGA micropump for gases and liquids. In: Sensors and Actuators A: Physical 40; p. 57–61. 1994.
[8] Pol van de FCM, Lintel van HTG, Elwenspoek M, Fluitman JHJ. A thermopneumatic micropump based on micro-engineering techniques. In: Sensors and Actuators A: Physical 21; p. 198–202. 1990.
[9] Zengerle R, Ulrich J, Kluge S, Richter M, Richter A. A bidirectional silicon micropump. In: Sensors and Actuators A: Physical 50; p. 81–6 1995.
[10] Walraven JA. Future Challenges for MEMS Failure Analysis. In: Proceedings of International Test Conference; p. 850-5. 2003.
[11] Li YB, Jiang ZB. An Overview of Reliability and Failure Mode Analysis of Microelectromechanical Systems (MEMS). In: Handbook of Performability Engineering; p. 953-66. 2008.
[12] Jeng YR, Tsai PC, Fang TH. Nanomeasurement and fractal analysis of PZT ferroelectric thin films by atomic force microscopy. In: Microelectronic Engineering 65; p. 406-15. 2003.
[13] Smith CA, Cole Jr EI. Resistive Contrast Imaging: A New SEM Mode for Failure Analysis. In: IEEE Transactions on Electron Devices Ed. 33: 2; p. 282-6. 1986.
[14] Walraven JA, Cole Jr EI, Tangyunyong P. Failure Analysis of MEMS Using Thermally-Induced Voltage Alteration, In: Proceedings from the 26th ISTFA; p. 489-96. 2000.
[15] Jang LS, Kan WH, Chen MK, Chou YM. Parameter extraction from BVD electrical model of PZT actuator of micropumps using time-domain measurement technique. In: Microfluidics and Nanofluidics 7; p. 559-68. 2009.
[16] Jeong OC, Park SW, Yang SS, Pak JJH. Fabrication of a peristaltic PDMSmicropump. In: Sensors and Actuators A: Physical 123–4; p. 453–8. 2005.
[17] Chou YM, Chen MK, Jang LS. Modified BVD Model of PZT Actuator by Time Domain Method for Micropump Application. In: Microfluidics and Nanofluidics 8; p. 727-38. 2009.
[18] Cheng JQ, Qian CF, Zhao MH, Lee, Tong P, Zhang TY. Effects of electric fields on the bending behavior of PZT-5H piezoelectric laminates. In: Smart Materials and Strutres 9; p. 824-31. 2000.
[19] Ueda S. Electromechanical response of a center crack in a functionally graded piezoelectric strip. In: Smart Materials and Strutres 14; p. 1133-8. 2005.
[20] Xu XL, Rajapakse RKND. Analytical solution for an arbitrarily oriented void/crack and fracture of piezoceramics. In: Acta Materialia 47; p. 1735-47. 1999.

------------------------------------------------------------------------ 第 9 筆 ---------------------------------------------------------------------
系統識別號 U0026-2806201101353700
論文名稱(中文) ANSYS應用在桿件元素之破壞分析
論文名稱(英文) Application of ANSYS to the Analysis of Failure for Bar Elements
校院名稱 成功大學
系所名稱(中) 土木工程學系碩博士班
系所名稱(英) Department of Civil Engineering
學年度 99
學期 2
出版年 100
研究生(中文) 羅際揚
學號 n66981177
學位類別 碩士
語文別 中文
口試日期 2011-06-15
論文頁數 110頁
口試委員 指導教授-徐德修
共同指導教授-朱世禹
口試委員-朱聖浩
關鍵字(中) 鋼架結構
ANSYS
有限元素法
斜撐桿件元素
破壞分析
關鍵字(英) steel frame
ANSYS
finite element method
bar element
failure analysis
學科別分類
中文摘要 由於電腦輔助分析軟體的成熟發展,使分析技術普遍被土木營造業所採用,除了提升建築結構的設計與強度外,更增加了建物的安全性。鋼架結構已廣泛應用於公共工程中,然而近年來,鋼材價格不斷飆漲,在成本考量下,強度高、安全性好的鋼架結構,便是設計考量的重要因素。鋼架內部的斜撐桿件可提高結構整體勁度,又可額外增加結構消能能力,因此斜撐桿件的斷面型式,以及裝設於鋼架上的位置,將影響到鋼架結構的行為表現。
本研究即是以電腦輔助分析軟體ANSYS Workbench來分析鋼架搭配上不同的斜撐桿件設計,共分成三部分進行,第一部分為參考公共設施的鋼架設計資料,再輔以ANSYS Workbench DesignModeler繪製鋼架及斜撐桿件模型;第二部分為利用有限元素軟體ANSYS Workbench進行結構應力及變位分析;第三部分為對鋼架結構之加載載重、破壞模式及變位量進行研究探討,藉以獲得較佳的斜撐設計。
英文摘要 Due to the highly development of the computer-aided technology, finite element method has being become as much more popular and commonly used in civil engineering applications. Safety and economy no doubt are the main concerns to engineers in the structural design process. For the purpose to investigate the behavior of the structural responses in detail, software package ANSYS is used herein for the simulation analysis. Rigid joint trusses are considered as axial-flexural bar element structures. Static analysis with refined finite element models is solved with members in various cross sections. Whole section yielding and member buckling are considered as the damage stages as the failure mode of the structures. It is believed that the methodology can be applied to structural optimal design problems to make the proper selection of members.
論文目次 摘要 Ⅰ
致謝 Ⅲ
目錄 Ⅴ
表目錄 Ⅷ
圖目錄 IX
第一章 緒論 1
1-1 研究動機與目的 1
1-2 研究方法 2
1-3 文獻回顧 4
1-4 章節提要 6
第二章 研究理論基礎 8
2-1有限元素法 8
2-2 ANSYS有限元素分析軟體 9
2-2.1 元素種類 10
2-2.2 結構分析 12
2-3 鋼斜撐的基本理論與強度分析 13
2-3.1 鋼材料應力-應變關係 13
2-3.2 降伏條件準則 15
2-4 拉力與壓力之破壞理論分析 16
2-4.1 拉力理論分析 16
2-4.2 壓力理論分析 17
2-4.3 彈性挫屈理論與非彈性挫屈理論 17
第三章 鋼架及桿件模型之規劃與模擬 21
3-1 鋼架及桿件基本材料特性 21
3-2 實體模型的建立 23
3-2.1 鋼架之設計尺寸及結構型式 23
3-2.2 斜撐桿件模型的建立 26
3-3 元素網格的劃分 35
3-3.1 使用之元素型式 35
3-3.2 網格分割 37
3-4 接觸元素的設定 46
3-5 邊界條件與載重的設定 47
3-6 結果顯示的設定 49
第四章 數值模擬分析結果 50
4-1 數值模擬之目標 50
4-2 數值模擬分析結果 50
4-2.1初始降伏點分析 50
4-2.2 結構破壞分析 68
4-2.3 卸載後殘留應力分析 85
第五章 結論與未來展望 103
5-1 結論 103
5-2 未來展望 105
參考文獻 106
自述 110
參考文獻 1.ANSYS, Inc., ANSYS Help System, version. 12.0.1, 2009.
2.Bathe, K. J., “Finite Element Procedures”, Prentice-Hall, Inc., New Jersey, 1996.
3.Becker, E. B., Carey, G. F., and Oden, J. T., “Finite Element: An Lnteroduction Volume I”, Prentice-Hall, Inc., New Jersey, 1981.
4.Bennett J. A., and Botkin M. E., “Structural Optimization Approach with Geometric Description and Adaptive Mesh Refinement”, AIAA Journal, Vol. 23, pp. 458, 1985.
5.Cheu T. C., “Procedures for Shape Optimization of Gas Turbine Disks”, Computers and Structures, Vol. 34, pp. 1, 1990.
6.Dirk Vollmer, Ulrich Meyer, Ulrich Joos, Andras Vegh,and Jozsef Piffko, “ Experimental and finite element study of a human mandible”, J. Cranio-Maxillofacial Surgery, Vol. 28, pp. 91, 2000.
7.Groth H. L., and Nordlund P., “Shape Optimization of Bonded Joints”, Int. J. Adhesion and Adhesives, Vol. 11, pp. 204, 1991.
8.Huei-Huang Lee,Finite Element Simulations With ANSYS Workbench 12 Theory-Applications-Case Studies,Schroff Development Corporation,2010.
9.Kamiya N., and Kita E., “Boundary Element Method for Quasi-harmonic Differential Equation with Application to Stress Analysis and Shape Optimization of Helical Spring”, Computers and Structures, Vol. 37, pp. 81, 1990.
10.Mahmood M. S., and Davood R., “Analysis and optimization of a composite leaf spring”, Composite Structures, Vol. 60, pp. 317, 2003.
11.Rao, S. S., 陳昭昌編譯,有限元素法-工程上之應用“The Finite Element Method in Engineering”,復文書局,1989.
12.Turner, M. J., Clough, R. W., Martin, H. C., and Topp, L. J., “Stifness and Deflection Analysis of Complex Structures”, Journal of Aeronautical Sciences, Vol. 23, 1956.
13.Zahavi E., “The Finite Element Method in Machine Design”, Prentice-Hall, 1992.
14.Zahavi, E., and Barlam, E., “Nonlinear Problems in Machine Design”, CRC Press LLC, 2000.
15.Zhu B., Rao B., Jia J., and Li Y., ”Shape optimization of Arch Dam for Static and Dynamic Loads”, J. Structural Engineering, Vol. 108, pp. 2996, 1992.
16.毛昭綱,材料力學,全華圖書,2008.05.
17.李輝煌,ANSYS工程分析基礎與觀念,高立圖書,2005.05.
18.林煒凱,有限元素ANSYS分析橢圓形凹槽薄壁管在循環彎曲負載下之力學行為,國立成功大學工程科學研究所碩士論文,2008.06
19.林敬銘,架空移動式起重機結構強度分析及桁架最佳化設計,國立成功大學機械工程學系碩士論文,2010.06.
20.高崇洋、王書龍及康淵,有限元素法在塔式起重機結構強度之分析,行政院勞工委員會勞工安全衛生研究所季刊,第6卷第4期,1998.12.
21.許豐榮,結構補強用斜撐之彈塑性行為數值模擬,國立中央大學土木工程學系碩士論文,2005.01.
22.楊詠超,引擎排氣歧管固定鉗之電腦輔助疲勞分析,逢甲大學航太與系統工程學系碩士論文,2007.07.
23.蔡國忠,ANSYS Workbench有限元素分析及工程應用,易習圖書,2011.04.
24.賴政忠,鋼筋混凝土梁柱構件於火害中強度評估之研究,國立成功大學土木工程學系碩士論文,2006.06.
25.蘇志彥,造型椅有限元素分析與設計,國立成功大學工程科學研究所碩士論文,2007.06.

 


如您有疑問,請聯絡圖書館
聯絡電話:(06)2757575#65773
聯絡E-mail:etds@email.ncku.edu.tw