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系統識別號 U0026-0309201011192600
論文名稱(中文) 結合SystemC TLM與雙核心之QEMU的異質整合架構之研究
論文名稱(英文) Integration of Heterogeneous Framework for SystemC TLM and Dual Core QEMU
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 98
學期 2
出版年 99
研究生(中文) 彭政軒
學號 n2697170
學位類別 碩士
語文別 中文
口試日期 2010-07-28
論文頁數 88頁
口試委員 指導教授-郭致宏
口試委員-李昆忠
口試委員-邱瀝毅
口試委員-陳春僥
關鍵字(中) 虛擬平台
TLM
SystemC
QEMU
雙核心系統
關鍵字(英) virtual platform
TLM
SystemC
QEMU
dual-core
學科別分類
中文摘要 由於電子電路製程技術的進步,讓單一晶片擁有更多不同的功能。單晶片的系統複雜化,使驗證單晶片系統的時間逐漸增加,更因此拖延產品的上市時間(Time to Market)。如何在系統設計初期即能夠驗證其功能性已成為重要的議題。
為了達到這個目標,本論文利用嵌入式虛擬平台的概念,提供一個驗證系統功能性的環境。相較於低抽象層級的RTL模型,以高抽象層級的TLM來建立系統將會更加快速且有效率。本論文利用SystemC程式語言建立以TLM為基礎的嵌入式虛擬平台,虛擬平台的架構規劃以真實開發版為基礎,建立具有良好的速度、靈活性與功能性的嵌入式虛擬平台。並依據這些基礎以改進虛擬平台的架構,如:提出模擬硬體中斷的機制,使SystemC所模擬的硬體能夠與QEMU使用者模式的CPU進行溝通;並在此CPU中實現大量傳輸資料的模式,以降低整體系統的模擬時間;估計QEMU所模擬之CPU操作頻率,令使用者在系統設計初期即能夠獲知軟體的運算複雜度,最後提出整合QEMU使用者模式之模擬雙核心CPU的方法,建立雙核心的虛擬平台,以提供雙核心系統設計初期時,能夠有快速驗證其功能性的虛擬平台。
英文摘要 With the advance of IC design technology, a single chip can have various functionalities. However, as the system complexity grows, the time for testing and approving a system on chip (SoC) also raises. How to evaluate the performance of a system in the early stages of design becomes an important issue in recent years.
To solve this problem, a virtual platform based verification method can help designers to reduce verification time during the development of a complex System on Chip (SoC) system. The effective way to speed up HW/SW co-simulation is to raise the abstraction levels from RTL to TLM. In this thesis, we use a SystemC based TLM and QEMU to implement a virtual platform that is built with speed, portable, and flexibility. According to these features, we increase the functionalities of the virtual platform with QEMU, including: hardware interrupt, burst mode transfer data, estimate the complexity of software and establish a dual core virtual platform.
論文目次 中文摘要 II
ABSTRACT III
誌謝 IV
表目錄 XI
第一章 緒論 1
1-1 研究動機 1
1-2 QEMU簡介 2
1-3 SystemC簡介 3
1-4 研究貢獻 4
1-5 論文架構 5
第二章 研究背景 6
2-1 研究背景 6
2-1-1 虛擬平台相關軟體 6
2-1-2 虛擬機器 8
2-1-3 虛擬平台之應用 9
2-2 相關論文研究 10
2-2-1 決定系統中硬體與軟體的抽象層級 11
2-2-2 不同抽象層級間之共同模擬方法 12
2-2-3 改善共同模擬之效能 14
2-2-4 MPSoC共同模擬之方法 17
2-2-5 研究文獻之探討 19
2-3 系統模擬層級─交易層級模型 20
2-4 CPU模擬器 – QEMU 22
2-4-1 QEMU的簡介及特性 22
2-4-2 QEMU的仿真模式 23
2-5 BSD SOCKET技術 25
2-5-1 Socket之阻塞與非阻塞傳輸模式 26
2-5-2 Socket之應用程式介面函式 27
2-5-3 客戶端與伺服端之間的連接範例 28
2-6 建立單核心虛擬平台之方法 30
2-6-1 修改QEMU的記憶體存取方式 31
2-6-2 系統匯流排模型之建立 33
2-6-3 Master與Slave Wrapper之建立 36
2-7 單核心虛擬平台的基本範例 39
第三章 QEMU虛擬平台之建立與功能之增進 41
3-1 實現QEMU使用者模式之中斷機制 42
3-1-1 QEMU模擬中斷機制之問題 43
3-1-2 QEMU於不同模式模擬中斷機制之方法 44
3-1-3 於QEMU使用者模式加入中斷機制之方法 45
3-2 支援QEMU使用大量傳輸資料模式 47
3-2-1 大量傳輸模式 47
3-2-1-1 大量寫入資料模式 48
3-2-1-2 大量讀取資料模式 50
3-2-1-3 大量傳輸範例:H.264/AVC解碼器 50
3-2-2 大量傳輸之模擬時間的同步 51
3-3 以運算複雜度評估QEMU模擬CPU效率之方法 53
3-3-1 QEMU模擬時間之計算 54
3-3-2 計算QEMU CPU所執行的MIPS 55
3-4 建立雙核心架構的虛擬平台 56
3-4-1 雙核心架構之背景 57
3-4-1-1 嵌入式系統開發版─PAC開發版 57
3-4-1-2 嵌入式系統開發版─達芬奇開發版 58
3-4-2 雙核心架構的虛擬平台之實現 61
3-4-2-1 仲裁控制機制 61
3-4-2-2 執行緒控制機制 63
第四章 實驗結果 66
4-1 中斷機制於虛擬平台之影響 66
4-1-1 使用socket次數對QEMU平台效率之影響 68
4-2 大量傳輸功能於虛擬平台之影響 70
4-3 估計QEMU使用者模式之CPU操作頻率 72
4-4 雙核心虛擬平台之模擬 74
4-4-1 平行處理機制於虛擬平台之建立 74
4-4-2 雙核心系統視訊解碼器程式於本實驗平台之應用 76
第五章 結論與未來展望 81

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系統識別號 U0026-0812200913351876
論文名稱(中文) 可組態之嵌入式軟體發展虛擬平台之設計與實作
論文名稱(英文) The Design and Implementation of a Configurable Virtual Platform for Developing Embedded Software
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 95
學期 1
出版年 96
研究生(中文) 王證詠
學號 Q3693106
學位類別 碩士
語文別 中文
口試日期 2006-07-06
論文頁數 90頁
口試委員 指導教授-陳敬
口試委員-楊中平
口試委員-林輝堂
口試委員-王明習
口試委員-薛智文
關鍵字(中) 模擬器
虛擬平台
嵌入式系統
可組態
關鍵字(英) virtual platform
simulation
emulation
embedded
學科別分類
中文摘要 本論文設計並實作一個具有可組態特性之的虛擬平台,用以模擬硬體開發板並使得嵌入式軟體可在這個虛擬平台上執行。此平台主要的特色可以增加虛擬開發板上各個元件在組合上的彈性及元件本身參數化能力(個數、種類、位址、大小等等),使得處理器、記憶體及週邊設備等元件可以用彈性的方式作選擇、參數設定,並加以配置。主要的方法是透過在模擬器裡增加一個中介者的角色,用以協調各模組的溝通,以減少各個模組之間的相依性,使得模組的加入、移除更為容易,藉此達到可組態的能力。
本虛擬平台主要包含四大部份:第一部份是提供介面組態、組態檔解析及配置等功能之前置處理程式;第二部份是對中央處理器(例如ARM7、ARM9等)、記憶體(ROM、RAM等)及週邊裝置的模擬;第三部份是圖形化使用操作介面(GUI)提供對模擬器的控制以及各種執行資訊的輸出及顯示;第四部份是為達到可組態的目標而設計的「模擬引擎」模組。模擬引擎為一中介者角色,是虛擬平台之架構的核心,用以處理中央處理器與記憶體及週邊之間的溝通。虛擬平台之執行分為三個階段:(1)配置:包含組態的選擇及解析,以解析後所得參數配置初始各個元件組合成虛擬開發板;(2)加載:載入待模擬程式碼至指定之記憶體位址中;(3)運行及除錯:虛擬開發板開始執行被模擬的程式,並可顯示程式被模擬執行的情形。虛擬平台的除錯功能提供中止、暫停、單步執行、斷點執行等控制,並可檢視處理器內部各暫存器、記憶體區塊內容、週邊裝置暫存器之內容變化。
在本平台所實作的構架下,彈性得到了改善。經由模擬執行許多程式進行測試,包括μCLinux作業系統皆可正常地運作於其上,也證實這個架構的適用性與可行性。
英文摘要 The subject of this thesis is the design and implementation of a configurable virtual platform for emulating the execution of embedded software. The primary feature of the platform is the improved flexibility in combining components and the parametric ability so that processor, memory blocks and I/O devices can be selected, set up with parameters and then configured to compose a desired virtual platform. The main approach to achieving the flexibility is adding an intermediary to coordinate the communications among the components. The inter-dependency among components is therefore reduced and a device can be added or removed more easily.
In the virtual platform, there are four parts: (1) the configuration processor which produces the configuration file, parses configuration information and initializes the configured components; (2) the emulation of processors, memory blocks (ROM and RAM) and I/O devices; (3) the GUI which displays the status of emulation and accepts user input; (4) the emulation engine, which is the core of the virtual platform, it handles the communication among the processor, memory blocks, and I/O devices and plays the role of intermediary. The operation is divided into three stages: (1) setting up: includes configuring, parsing, and setting up the virtual platform according to the configuration parameters; (2) loading: loading a file at a specified memory address; (3) execution: emulating the execution of program and display useful information. The virtual platform offers debugging features such as stop, pause, step by step, and break point, etc. User can monitor the processor registers, the content of memories, and the registers of I/O devices.
The virtual platform is implemented and its functionality is validated. Many programs including the μCLinux operating system can correctly execute via the emulation. The suitability and feasibility of this approach therefore are proved.
論文目次 第1章 緒 論 1
1.1 前言 1
1.2 背景知識 1
1.2.1 仿真模擬(Emulation)與模擬(Simulation)的差異 1
1.2.2 模擬目標的分類 2
1.2.3 純軟體模擬與非純軟體模擬 3
1.3 研究動機及目的 4
1.4 研究方法 5
1.5 章節規劃 5
第2章 相關研究 6
2.1 處理器模擬的種類 6
2.1.1 直譯式指令集模擬(Interpreting Emulation) 7
2.1.2 轉譯式二進制碼轉換(Binary Translation) 8
2.2 實例探討 13
2.2.1 GDB/ARMulator 13
2.2.2 SkyEye 14
2.2.3 WuKong 15
第3章 模擬平台之架構與實作 17
3.1 模擬平台架構 17
3.2 開發板模擬器整體架構 18
3.3 系統級模擬執行流程 19
3.4 處理器的模擬 20
3.5 記憶體的模擬 21
3.6 週邊裝置的模擬 25
3.6.1 週邊裝置的硬體行為特性 26
3.6.2 週邊裝置通用結構 27
3.6.3 週邊裝置之諸元 28
3.7 週邊裝置的輔助工具 33
3.8 模擬引擎(Emulation Engine) 37
3.8.1 角色及功能 37
3.8.2 模擬引擎與處理器的溝通介面 40
3.8.3 模擬引擎與記憶體的溝通介面 41
3.8.4 模擬引擎與週邊裝置的溝通介面 41
3.9 同步與時序控制機制 43
3.9.1 處理器與週邊裝置之執行比例 43
3.9.2 週邊裝置週期性工作的安排與執行 44
3.10 系統環境 45
第4章 可組態性及擴充性 46
4.1 組態介面及組態檔 46
4.2 組態解析及配置流程 49
4.3 擴充性 52
4.3.1 處理器的擴充 52
4.3.2 記憶體及週邊裝置的擴充 53
第5章 模擬平台之使用說明及測試程式 55
5.1 功能簡介及使用說明 55
5.1.1 組態設定(Configuration) 56
5.1.2 執行檔載入(File) 60
5.1.3 執行與除錯(Execute and Debug) 60
5.1.4 資訊顯示(View) 62
5.1.5 工具(Utility) 65
5.1.6 記錄(Log) 66
5.2 驗證與測試程式 68
第6章 結論與展望 85
6.1 結論 85
6.2 展望與未來工作 85
參 考 文 獻 87
自述 90
參考文獻 參 考 文 獻
[1] μCLinux org, ”μCLinux in the GDB/ARMulator”,
http://www.uclinux.org/pub/uClinux/utilities/armulator/.
[2] GDB, ” The GNU Project Debugger”, http://www.gnu.org/software/gdb/.
[3] Victor Moya del Barrio, Agustin Fernandez, “Study of the techniques
for emulation Programming”.
[4] Marat Fayzullin, “How To Write a Computer Emulator”
http://fms.komkon.org/EMUL8/HOWTO.html.
[5] “Emulators-FAQ”, http://www.faqs.org/faqs/emulators-faq/.
[6] ARM, ”ARM architecture reference manual 2nd edition“, ARM Inc.
[7] ARM, “ARM7DMI(rev4) Technical reference manual”, ARM Inc.
[8] SimOS, “The Complete Machine Simulator”,
http://simos.stanford.edu/.
[9] IBM Austin Research lab, ” SimOs-PPC”,
http://www.cs.utexas.edu/~cart/simOS/documents.htm.
[10] IBM tech doc, “Validation of a Full System Simulator”,
http://www.research.ibm.com/journal/rd/502/peterson.html.
[11] Bochs project, ”Open source IA-32 (x86) PC emulator”,
http://bochs.sourceforge.net/.
[12] DebianWiki, “Bochs How to”,
http://www.debian.org.tw/index.php/Bochs.
[13] QEMU project, ”An open source processor emulator which achieves a
good emulation speed by using dynamic translation.”,
http://fabrice.bellard.free.fr/qemu/.
[14] Plex86 project, ”Offer a very lightweight Virtual Machine (VM) for
running Linux/x86”, http://plex86.sourceforge.net/.
[15] Virtutech simics project, ”Commercial simulator that can target
IA32, IA64, Sparc, Alpha, ARM, PowerPC, and MIPS architectures”,
http://www.virtutech.com/products/.
[16] VmWare project, ”A commercial virtual PC type system for Linux and
Windows-based PC's”, http://www.vmware.com/.
[17] Virtual PC, ”A commercial virtual PC implementation”,
http://www.microsoft.com/windows/virtualpc/previous/default.mspx.
[18] MAME, ”Multiple Arcade machine emulator”, http://www.mame.net/.
[19] SimIt-ARM, ”ARM processor emulator”, http://simit-
arm.sourceforge.net/.
[20] SWarm (Soft Ware ARM), ”ARM processor emulator”,
http://www.swarm.org/wiki/Main_Page.
[21] SimpleScalar, “A system software infrastructure used to build
modeling applications for program performance analysis, detailed
microarchitectural modeling, and hardware-software co-verification”,
http://www.simplescalar.com/.
[22] Just-in-time compilation, “A dynamic translation technique”,
http://en.wikipedia.org/wiki/Just-in-time_compilation.
[23] Bytecode, “A sort of intermediate code”,
http://en.wikipedia.org/wiki/Bytecode.
[24] Hitachi, “HD66750/1(128 x 128-dot Graphics LCD Controller/Driver
with Four-grayscale Functions) Rev 0.7”, July 26th, 1999.
[25] Alfred V.Aho, Ravi Sethi, Jeffrey D.Ullman, “Compilers Principles,
Techniques, and Tools”, ISBN:0-201-10194-7, Addison-Wesley
publishing company.
[26] 新華電腦, “ARM內嵌式SOC原理(以ARM7DMI S3C4510B為例)”, ISBN: 957-21-
4520-7, Jan. 2004,全華科技出版。
[27] 新華電腦, “ARM內嵌式SOC實作(以ARM7DMI S3C4510B為例)”, ISBN:957-21-
4524-X, Jan. 2004,全華科技出版。
[28] 新華電腦, “Embedded uClinux在PreSOCes上實作”, ISBN:957-21-5191-6,
Jan. 2004,全華科技出版。
[29] SkyEye, ”Embedded system simulator project”, 北京清華大學計算機系,
2002, http://www.huihoo.org/mirrors/skyeye/.
[30] WuKong, ”Embedded system simulator project”, 浙江大學嵌入式
系統軟件研發中心,杭州,2004, http://embedded.zju.edu.cn/wukong/.

------------------------------------------------------------------------ 第 3 筆 ---------------------------------------------------------------------
系統識別號 U0026-1308201020364000
論文名稱(中文) 支援GDB之指令集架構模擬器與其全系統虛擬平台
論文名稱(英文) An Instruction Set Simulator with GDB Support and its Full System Simulation Virtual Platform
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 98
學期 2
出版年 99
研究生(中文) 李信穎
學號 q3697402
學位類別 碩士
語文別 英文
口試日期 2010-07-14
論文頁數 60頁
口試委員 指導教授-陳中和
口試委員-謝錫堃
口試委員-邱瀝毅
口試委員-黃穎聰
關鍵字(中) 虛擬平台
全系統模擬
協同模擬
系統除錯
關鍵字(英) virtual platform
full system simulation
co-simulation
system debugging
學科別分類
中文摘要 在晶片系統的開發過程中,如何在全部的硬體裝置開發完成前即進行系統軟體的開發以及軟硬體的協同模擬與協同驗證,是晶片系統開發人員一直以來所面臨的一大挑戰。
在本論文中,我們利用SystemC模組實現了一個基於ARM架構的指令集模擬器與其全系統虛擬平台。此SystemC虛擬平台提供了功能準確性以及時間準確性的全系統模擬環境。藉由此SystemC虛擬平台,系統開發工程師能夠很容易地對整體晶片系統(包含:硬體裝置、作業系統、驅動程式、以及應用程式…等部件)進行協同模擬、協同驗證、系統評測與演算法分析的工作。除此之外,此虛擬平台亦內建了GDB遠端除錯協定的通訊通道。透過此遠端除錯通道,SystemC虛擬平台可直接與GDB除錯器進行連接,便於軟體工程師利用此虛擬平台和我們所修改擴充的naked GDB除錯器於系統開發先期即開始進行各種系統軟體與應用程式的開發及除錯工作,以達到有效地縮短整體晶片系統開發時程的目標。
英文摘要 When developing a system-on-a-chip (SoC) embedded system, how to develop the system software as well as co-verify the hardware and software before all hardware modules are available is usually a big challenge for engineers.
In this thesis, we have implemented a virtual platform with an ARM-based instruction set simulator in SystemC. This virtual platform provides a functional and/or approximate-timed accurate full system simulation environment. By this SystemC virtual platform, SoC developers are able to co-simulate, co-verify, evaluate, and analyze the whole SoC system including hardware devices, OS kernel, device drivers, and application programs…etc., in a simple way. Also, we have provided a GDB RDP communication channel to connect the virtual platform and GDB debugger directly. Through this virtual platform and the naked GDB debugger which we modify from GDB, software engineers can easily develop and debug the system programs in the early development stage. Thus, the time-to-market of a new SoC design can be reduced significantly.
論文目次 摘要 I
Abstract II
Contents III
List of Figures VI
List of Tables VIII
Chapter 1 - Introduction 1
1.1 Motivation 1
1.2 Contribution 2
1.3 Scope and Organization 3
Chapter 2 - Background and Related Works 4
2.1 Instruction Set Simulator 4
2.1.1 Interpretive Simulation 4
2.1.2 Static Compiled Simulation 5
2.1.3 Dynamic Compiled Simulation 6
2.2 GNU Debugger 7
2.2.1 Introduction to GDB 7
2.2.2 Remote Debugging Protocol 8
2.3 Related Works 10
2.3.1 Simplescalar 10
2.3.2 FaCSim 10
2.3.3 Dynamic Binary Translation 11
2.3.4 SimIt-ARM 12
2.3.5 Hybrid Compiled Simulation 12
2.3.6 Simics 13
Chapter 3 - System Framework 14
3.1 Emulation Methodology 14
3.1.1 The Accurate Model 14
3.1.2 SystemC Simulation Methodologies 16
3.2 ARM-Based Instruction Set Simulator 18
3.2.1 Datapath 18
3.2.2 Memory System 20
3.2.3 Exception Handlers 20
3.3 Naked GDB 21
3.3.1 The Virtual Platform with GDB 21
3.3.2 Co-processor Probing 22
3.4 Power Estimation of the Memory System 23
3.5 The SystemC Virtual Platform 25
3.5.1 Platform Overview 25
3.5.2 Full System Simulation 27
3.5.3 Evaluation Methodology 31
Chapter 4 - Platform Verification 33
4.1 Verification Methodology 33
4.2 Linux Booting Sequence 34
4.3 Verification Result 35
4.3.1 Verification by Linux Booting 35
4.3.2 Verification by Device Driver under Linux 38
4.3.3 Verification by User Mode Applications under Linux 39
4.3.4 Co-Work with the Naked GDB 41
4.3.5 Summary of System Verification 42
Chapter 5 - Evaluation and Results 43
5.1 Experimental Environment and Parameters 43
5.2 Simulation Performance 45
5.2.1 The Throughput 45
5.2.2 SystemC Speedup 47
5.3 Cycles per Instruction 48
5.4 Power Metric 49
5.5 Profiling of Linux Booting Sequence 51
Chapter 6 - Conclusions 55
Chapter 7 - Future Works 56
References 57
參考文獻 [1] “PrimeCell Color LCD (PL110) Technical Reference Manual DDI-0161E,” ARM Co. Ltd., May 2003.
[2] “ARM Dual-Timer Module (SP804) Technical Reference Manual,” ARM Co. Ltd., January 2004.
[3] “ARM926EJ-S Technical Reference Manual DDI-0198D,” ARM Co. Ltd. January 2004.
[4] “PrimeCell Vectored Interrupt Controller (PL190) Technical Reference Manual DDI-0181E” ARM Co. Ltd., November 2004.
[5] “ARM Architecture Reference Manual DDI-0100I,” ARM Co. Ltd., July 2005.
[6] “PrimeCell UART (PL011) Technical Reference Manual DDI-0183F,” ARM Co. Ltd., November 2005.
[7] “Versatile Application Baseboard for ARM926EJ-S User Guide DUI-0225B,” ARM Co. Ltd., July 2006.
[8] “IEEE Standard SystemC Language Reference Manual,” Design Automation Standards Committee, IEEE Computer Society, March 2006.
[9] J. R. Andrews, “Co-Verification of Hardware and Software for ARM SoC Design,” Elsevier Inc., August 2004.
[10] D. Beal, “The Magic of Virtualized Systems Development,” Virtutech Co. Ltd., October 2009.
[11] D. C. Black, J. Donovan, B. Bunton, and A. Keist, “SystemC: From the Ground up 2nd Edition,” Springer Media Inc., 2010.
[12] D. P. Bovet and M. Cesati, “Understanding the Linux Kernel 3rd Edition,” O’Reilly Media Inc., November 2005.
[13] D. Burger and T. M. Austin, “The Simplescalar Tool Set Version 2.0,” University of Wisconsin-Madison Computer Sciences Department Technical Report, June 1997.
[14] F. Bellard, “QEMU, a Fast and Portable Dynamic Translator,” Proceedings of the 2005 USENIX Annual Technical Conference, Anaheim, CA, USA, April 2005.
[15] L. Charest, C. Pilking, and P. Paulin, “SystemC Performance Evaluation Using a Pipelined DLX Multiprocessor,” Proceedings of the 2002 ACM/IEEE Design, Automation, & Test in Europe Conference (DATE’02), Paris, France, March 2002.
[16] J. Corbet, A. Rubini, and G. Kroah-Hartman, “Linux Device Driver 3rd Edition”, O’Reilly Media Inc., January 2005.
[17] J. Gilmore and S. Shebs, “GDB Internals—A Guide to the Internals of the GNU Debugger,” Cygnus Solutions, February 2004.
[18] T. Grötker, S. Liao, G. Martin, and S. Swan, “System Design with SystemC,” Springer Media Inc., 2002.
[19] M. R. Guthaus, et al., “MiBench: a Free, Commercially Representative Embedded Benchmark Suite,” Proceedings of the 2008 IEEE International Workshop on Workload Characterization (WWC’01), Austin, TX, USA, December 2001
[20] A. H. Han, Y.-S. Hwang, Y.-H. An, S.-J. Lee, and K.-S. Chung, “Virtual ARM Platform for Embedded System Developers,” Proceedings of the 2008 IEEE International Conference on Audio, Languages, and Image Processing (ICALIP’08), pp. 586-592, Shanghai, China, November 2008.
[21] H.-W. Kao, “Embedded Processor Verification Using Particular Characteristics of Linux Operating System,” 2006 master thesis of National Cheng Kung University, Tainan, Taiwan, July 2006.
[22] J. Lee, et al., “FaCSim: A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems,” Proceedings of the 2008 ACM SIGPLAN-SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’08), pp. 89-100, Tucson, AZ, USA, June 2008.
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[24] P. Ezudheen, et al., “Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines,” Proceedings of the 23rd ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS’09), pp. 80-87, Lake Placid, NY, USA, June 2009.
[25] J. Montanaro, et al., “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1703-1714, November 1996.
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[27] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A Tool to Model Large Caches,” HP Laboratories, April 2009.
[28] M. Reshadi, P. Mishara, and N. Dutt, “Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation,” Proceedings of the 40th ACM/IEEE Design Automation Conference (DAC’03), Vol. 8, No. 3, pp. 758-763, Anaheim, CA, USA, June 2003.
[29] M. Reshadi and N. Dutt, “Reducing Compilation Time Overhead in Compiled Simulators,” Proceedings of the 21st IEEE Internaional Conference on Computer Design (ICCD’03), pp. 151-153, San Jose, CA, USA, October 2003.
[30] M. Reshadi, P. Mishara, and N. Dutt, “Hybrid-Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation,” ACM Transactions on Embedded Computer Systems, Vol. 8, No. 3, pp. 20-27, April 2009.
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[34] R. Stones and N. Matthew, “Beginning Linux Programming 3rd Edition,” Wiley Publishing Inc., January 2004.

------------------------------------------------------------------------ 第 4 筆 ---------------------------------------------------------------------
系統識別號 U0026-2608201016353000
論文名稱(中文) GDB移植於實體與虛擬平台-應用於多核心虛擬平台
論文名稱(英文) GDB Porting on Virtual and Physical Platforms with Application to Multi-core OpenSPARC Virtual Platform
校院名稱 成功大學
系所名稱(中) 資訊工程學系碩博士班
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 98
學期 2
出版年 99
研究生(中文) 方品皓
學號 p7697438
學位類別 碩士
語文別 中文
口試日期 2010-07-26
論文頁數 95頁
口試委員 口試委員-吳安宇
口試委員-鄭芳炫
口試委員-陳中和
口試委員-張大緯
指導教授-蘇文鈺
關鍵字(中) GDB
8051
debugging stub
擬真器
多核心
虛擬平台
關鍵字(英) GDB
8051
debugging stub
emulator
multi-core
virtual platform
學科別分類
中文摘要 本篇論文為實做GDB對單核心和多核心架構進行除錯,並且可以隨著處理器的發展,與不同階段的發展平台相連。單核心方面,我們實做出英特爾 8051單晶片的除錯器,其主要內容包括在GDB增加8051的架構、實做多種除錯指令、和針對多種8051平台進行遠端除錯。由於8051平台需要debugging stub負責與GDB溝通並執行其指令,所以根據不同的處理器發展階段,針對不同的8051平台建立debugging stub;CPU平台的debugging stub為一段函式,需要與被除錯的程式一起編譯成執行檔載入目標機器;擬真器平台的debugging stub為一個外部模組,做為擬真器和GDB溝通的橋梁;虛擬平台的debugging stub則能沿用以上任一種。另外在多核心方面,我們提出一個多核心的虛擬平台,Multi-SPARC虛擬平台,其單核心為開放源碼的SPARC V8 架構。為了增加其模擬效能,本虛擬平台在ESL等級下進行模擬。我們定義一些特定的函式進行資料溝通,並建立了TLM介面使其他外部模組可以透過此介面與多核心虛擬平台做溝通。我們提出的多核心系統能夠同時與多個SPARC v8 GDB進行除錯,測試多個應用程式證明其可行性,並且模擬效能比RTL快約1000倍。
英文摘要 We implement porting the GNU GDB to new target machines, including single core and multi-core architecture, and present on different platforms according to stages of processor development. We present the Intel 8051 debugger by define the 8051 architecture in GDB which can perform several debugging commands and remote debugging with 8051 platforms. As the need of debugging stub for 8051 platform to communicate with GDB, the stubs need to implement respectively with different development stages of processor platform; For CPU platform, it has to compile with application into image file executed on target machine; For emulator, it present as an external model connecting with both GDB and emulator; For virtual platform, any of the above two can put in good use. Furthermore, we present a multi-core virtual platform, Multi-SPARC virtual platform, which follows single-core architecture, SPARC v8, available as an open source development suite. To accelerate the simulation speed, the proposed platform is performed at electronic system level (ESL) in SystemC. We define some specific APIs for data transaction and implement the TLM interface for external modules to communicate with the host virtual platform. The proposed multi-SPARC system is able to connect with many SPARC v8 GDB, the same one which is predefine in GDB. We used several benchmarks to test its correctness, and it simulation speed can be 1000 times faster than RTL’s.
論文目次 中文摘要 iv
Abstract v
誌謝 vii
Content viii
List of Tables x
List of Figures xi
Chapter 1 介紹 1
1.1. 動機 3
1.2. 論文架構 4
Chapter 2 GDB 介紹與移植 5
2.1. GDB內部架構的介紹 6
2.2. 在GDB內加入新處理器 9
2.2.1. 定義目標除錯格式 (BFD) 9
2.2.2. 定義目標架構 10
2.3. 遠端除錯 10
2.4. 遠端連線協定 (RSP) 11
2.4.1. 連接到目標機器 12
2.4.2. Debugging stub 12
Chapter 3 移植8051架構到GDB 14
3.1. Intel 8051 14
3.1.1. 8051架構介紹 14
3.1.2. 8051 發展工具 15
3.1.3. 8051 程式執行平台 16
3.2. 建立8051除錯器 17
3.3. 建立 8051 debugging stub 18
3.3.1. Debugging stub於8051 CPU 19
3.3.2. Debugging stub於8051 擬真器 23
3.3.3. Debugging stub於8051 虛擬平台 26
Chapter 4 Multi-SPARC 虛擬平台 30
4.1. Multi-SPARC 虛擬平台簡介 30
4.2. 單核心指令模擬器 30
4.2.1. 處理器架構-SPARC 31
4.2.2. ArchC 31
4.2.3. 系統設計與驗證語言-SystemC 33
4.2.4. 電子系統層級(ESL) 34
4.3. Multi-SPARC虛擬平台的建立 35
4.3.1. 多核心架構 35
4.3.2. 溝通介面 36
4.3.3. 應用程式的資料傳遞 38
4.3.4. 應用程式的效能評估 39
4.4. Multi-SPARC虛擬平台的外部控制 39
4.4.1. 控制介面 39
4.4.2. 動態載入 40
4.5. Multi-SPARC虛擬平台的發展工具 41
4.6. 實驗結果 44
4.4.1. 4-SPARC 虛擬平台與4個GDB連線 45
4.4.2. 應用程式的驗證 47
Chapter 5 結論與未來展望 55
參考文獻 57
附錄A. GDB安裝與使用 59
附錄B. 實做8051架構至GDB的移植 66
附錄C. Debugging Stub for Each Platform 77
附錄D. 多核心虛擬平台-ESL與RTL的效能比較 93
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[ 2] Intel® Microcontrollers. Available: http://www.intel.com/design/embcontrol/index.htm
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[ 4] Brian Bailey, Grant Martin and Andrew Piziali, “ESL Design and Verification: A Prescription for Electronic System Level Methodology”. Morgan Kaufmann/Elsevier, 2007
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[ 17]Synopsys VCS. Available: http://www.synopsys.com
[ 18] MICROCONTROLLER TUTORIALS – 8051. Available: http://www.hobbyprojects.com/8051_tutorial/special_function_registers.html

 


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